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| cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 15051 rev. *i revised july 1, 2 016 the following document contains information on cypress products. although the document is marked with the name broadcom , the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the ordering part numbers listed in this document. for more information please visit our website at www .cypress.com or contact your local sales office for additional information about cypress pro ducts and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create n ew industries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated pro ducts and get them to market first. cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record tim e. to learn more, go to www.cypress.com .
43455-ds109-r 5300 california avenue ? irvine, ca 92617 ? phone: 949-926-5000 ? fax: 949-926-5203 november 5, 2015 preliminary data sheet BCM43455 single-chip 5g wifi ieee 802.11ac mac/baseband/ radio with integrated bluetooth 4.1 and fm receiver figure 1: functional block diagram general description the broadcom ? BCM43455 single-chip device provides the highest level of integration for a mobile or handheld wireless system with integrated single- stream ieee 802.11ac mac/baseband/radio, bluetooth 4.1,and fm receiver. in ieee 802.11ac mode, the wlan operation supports rates of mcs0?mcs9 (up to 256 qam) in 20 mhz, 40 mhz, and 80 mhz channels for data rates of up to 433.3 mbps. all rates specified in the ieee 802.11a/b/g/n are supported. included on-chip are 2.4 ghz and 5 ghz transmit amplifiers and receive low-noise amplifiers. optional external pas and lnas are also supported. the wlan section supports the following host interface options: an sdio v3.0 interface that can operate in 4b or 1b mode, a high-speed 4-wire uart, and a pcie gen1 (3.0 compliant) interface. the bluetooth section supports a high-speed 4-wire uart interface. using advanced design techniques and process technology to reduce active and idle power, the BCM43455 is designed to address the needs of mobile devices that require minimal power consumption and compact size. it includes a power management unit which simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life. the BCM43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which ensure that wlan and bluetooth collaboration is optimized for maximum performance. in addition, coexistence support for external radios (such as lte cellular and gps) is provided via an external interface. as a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. fem or t/r switch vio vbat 5 ghz wlan tx 5 ghz wlan rx 2.4 ghz wlan tx 2.4 ghz wlan/bt rx bluetooth tx fm rx wlan host i/f bluetooth host i/f fm rx host i/f wl_reg_on sdio pcie bt_reg_on uart bt_dev_wake bt_host_wake cbf i 2 s fm audio out i 2 s pcm coex external coexistence i/f fem or optional t/r switch fm i/f uart BCM43455 revision history BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 2 broadcom confidential features ieee 802.11x key features ? ieee 802.11ac compliant. ? support for turboqam ? (mcs0?mcs8 86 mbps and mcs0?mcs9 96 mbps) ht20, 20 mhz channel bandwidth. ? single-stream spatial multiplexing up to 433.3 mbps data rate. ? supports 20, 40, and 80 mhz channels with optional sgi (256 qam modulation). ? full ieee 802.11a/b/g/n legacy compatibility with enhanced performance. ? supports explicit ieee 802.11ac transmit beamforming. ? tx and rx low-density parity check (ldpc) support for improved range and power efficiency. ? on-chip power amplifiers and low-noise amplifiers for both bands. ? support for optional front-end modules (fem) with external pas and lnas. ? supports optional integrated t/r switch for 2.4 ghz band. ? supports rf front-end architecture with a single dual-band antenna shared between bluetooth and wlan for lowest system cost. ? shared bluetooth and wlan receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both bluetooth and wlan. ? internal fractional-n pll allows support for a wide range of reference clock frequencies. ? supports ieee 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as lte or gps. ? supports standard sdio v3.0 (including ddr50 mode at 50 mhz and sdr104 mode at 208 mhz, 4-bit and 1-bit) interfaces. bluetooth key features ? complies with bluetooth core specification version 4.1 with provisions for supporting future specifications. ? bluetooth class 1 or class 2 transmitter operation. ? supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets. ? adaptive frequency hopping (afh) for reducing radio frequency interference. ? interface support, host controller interface (hci) using a high-speed uart interface and pcm for audio data. ? fm unit supports hci for communication. ? fm receiver: 65 mhz to 108 mhz fm bands; supports the european radio data systems (rds) and the north american radio broadcast data system (rbds) standards. ? low power consumption improves battery life of handheld devices. ? supports multiple simultaneous advanced audio distribution profiles (a2dp) for stereo sound. ? automatic frequency detection for standard crystal and tcxo values. general features ? supports battery voltage range from 3.0v to 5.25v supplies with internal switching regulator. ? programmable dynamic power management ? 6 kbit otp for storing board parameters. ?gpios: 15 ? 140-ball wlbga package (4.47 mm 5.27 mm, 0.4 mm pitch). ? broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation all rights reserved printed in the u.s.a. broadcom ? , the pulse logo, connecting everything ? , the connecting everything logo, onedriver ? , smartaudio ? , and turboqam ? are among the trademarks of broadcom corporation and/or its affiliates in the united states, certain other countries and/or the eu. any other trademarks or trade names mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. broadcom provides this data sheet ?as-is,? without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitnes s for a particular purpose, and non- infringement. features ieee 802.11x key features (cont.) ? backward compatible with sdio v2.0 host interfaces. ? pcie mode complies with pci express base specification revision 3.0 compliant gen1 interface for 1 lane and power management base specification. ? integrated armcr4 processor with tightly coupled memory for complete wlan subsystem functionality and minimizing the need to wake-up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. on-chip memory includes 800 kb sram and 704 kb rom. ? onedriver ? software architecture for easy migration from existing embedded wlan and bluetooth devices as well as future devices. general features (cont.) ? security: ? wpa and wpa2 (personal) support for powerful encryption and authentication ? aes and tkip in hardware for faster data encryption and ieee 802.11i compatibility ? reference wlan subsystem provides cisco compatible extensions (ccx, ccx 2.0, ccx 3.0, and ccx 4.0) ? reference wlan subsystem provides wi-fi protected setup (wps) ? worldwide regulatory support: global products supported with worldwide homologated design. revision history BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 4 broadcom confidential revision history revision date change description 43455-ds109-r 11/05/15 updated: ? table 17: ?wlbga pin list by pin number,? on page 81 . ? table 18: ?wlbga pin list by pin name,? on page 83 . ? table 19: ?signal descriptions,? on page 85 . 43455-ds108-r 09/25/15 updated: ? figure 55: ?140-ball wlbga package mechanical information,? on page 24: nominal height (a) is 0.55 mm. 43455-ds107-r 07/29/15 updated: ? figure 56: ?140-balls wlbga keep-out areas for pcb layout ?top view with balls facing down,? on page 169 43455-ds106-r 07/09/15 updated: ? table 22: ?wlbga signal descriptions,? on page 97. ? table 26: ?i/o states,? on page 106. ? table 37: ?wlan 2.4 ghz receiver performance specifications,? on page 125. ? table 39: ?wlan 5 ghz receiver performance specifications,? on page 130. ? figure 56: ?140-balls wlbga keep-out areas for pcb layout?top view with balls facing down,? on page 168. 43455-ds105-r 04/06/15 updated: ? table 36: ?wlan 2.4 ghz transmitter performance specifications,? on page 122. ? table 38: ?wlan 5 ghz transmitter performance specifications,? on page 128. revision history BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 5 broadcom confidential 43455-ds104-r 03/31/15 updated: ? ?jtag/swd interface? on page 73. ? table 22: ?wlbga signal descriptions,? on page 97: wlan gpio interface and jtag interface. ? table 29: ?esd specifications,? on page 110. ? table 31: ?bluetooth receiver rf specifications,? on page 113. ? table 32: ?bluetooth transmitter rf specifications,? on page 116. ? table 33: ?local oscillator performance,? on page 118. ? table 34: ?ble rf specifications,? on page 118. ? table 36: ?2.4 ghz band general rf specifications,? on page 125. ? table 37: ?wlan 2.4 ghz receiver performance specifications,? on page 125. ? table 38: ?wlan 2.4 ghz transmitter performance specifications,? on page 129. ? table 40: ?wlan 5 ghz transmitter performance specifications,? on page 135. ? ?transmitter spurious emissions specifications? on page 137. ? section 18: ?internal regulator electrical specifications,? on page 141. ? table 53: ?2.4 ghz mode wlan power consumption,? on page 147. ? table 54: ?5 ghz mode wlan power consumption,? on page 148. ? table 55: ?bluetooth and ble current consumption,? on page 149. added: ? ?swd timing? on page 161. revision date change description revision history BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 6 broadcom confidential 43455-ds103-r 02/04/15 updated: ? ?external coexistence interface? on page 72. ? table 31: ?bluetooth receiver rf specifications,? on page 113. ? table 32: ?bluetooth transmitter rf specifications,? on page 116. ? table 33: ?local oscillator performance,? on page 118. ? table 34: ?ble rf specifications,? on page 118. ? table 35: ?fm receiver specifications,? on page 119. ? table 37: ?wlan 2.4 ghz receiver performance specifications,? on page 125. ? table 38: ?wlan 2.4 ghz transmitter performance specifications,? on page 128. ? table 39: ?wlan 5 ghz receiver performance specifications,? on page 129. ? table 40: ?wlan 5 ghz transmitter performance specifications,? on page 133. ? table 42: ?2.4 ghz band, 20 mhz channel spacing tx spurious emissions specifications,? on page 135. ? table 43: ?5 ghz band, 20 mhz channel spacing tx spurious emissions specifications,? on page 136. ? table 44: ?5 ghz band, 40 mhz channel spacing tx spurious emissions specifications,? on page 137. ? table 45: ?5 ghz band, 80 mhz channel spacing tx spurious emissions specifications,? on page 138. ? table 46: ?2g and 5g general receiver spurious emissions,? on page 139. ? table 53: ?2.4 ghz mode wlan power consumption,? on page 146. ? table 54: ?5 ghz mode wlan power consumption,? on page 147. 43455-ds102-r 11/20/14 updated: ? table 26: ?esd specifications,? on page 104. 43455-ds101-r 11/06/14 updated: ? figure 3: ?typical power topology (page 1 of 2),? on page 22 and figure 4: ?typical power topology (page 2 of 2),? on page 23. ? figure 38: ?port locations for bluetooth testing,? on page 109. ? figure 39: ?port locations for wlan testing,? on page 121. 43455-ds100-r 10/27/14 initial release. revision date change description table of contents BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 7 broadcom confidential table of contents about this document ............................................................................................................................... .17 purpose and audience ........................................................................................................... ............... 17 acronyms and abbreviations..................................................................................................... ............ 17 document conventions ........................................................................................................... .............. 17 references ..................................................................................................................... ....................... 17 technical support ............................................................................................................................... ....... 18 section 1: BCM43455 overview ....................................................................................... 19 overview ............................................................................................................................... ....................... 19 standards compliance ............................................................................................................................... 21 mobile phone usage model ....................................................................................................................... 22 section 2: power supplies and power management ..................................................... 23 power supply topology ............................................................................................................................. 23 BCM43455 pmu features .......................................................................................................................... 23 wlan power management ........................................................................................................................ 26 pmu sequencing ............................................................................................................................... ......... 26 power-off shutdown ............................................................................................................................... ... 27 power-up/power-down/reset circuits ..................................................................................................... 28 section 3: frequency references.................................................................................... 29 crystal interface and clock generation ................................................................................................... 29 external frequency reference .................................................................................................................. 30 frequency selection ............................................................................................................................... ... 32 external 32.768 khz low-power oscillator .............................................................................................. 33 section 4: bluetooth and fm subsystem overview....................................................... 34 features ............................................................................................................................... ........................ 34 bluetooth radio ............................................................................................................................... ........... 36 transmit ....................................................................................................................... ......................... 36 digital modulator .............................................................................................................. ..................... 36 digital demodulator and bit synchronizer....................................................................................... ...... 36 power amplifier ................................................................................................................ ..................... 36 receiver ....................................................................................................................... ......................... 37 digital demodulator and bit synchronizer....................................................................................... ...... 37 receiver signal strength indicator............................................................................................. ........... 37 local oscillator generation .................................................................................................... ............... 37 calibration .................................................................................................................... ......................... 37 section 5: bluetooth baseband core .............................................................................. 38 bluetooth 4.0 features ............................................................................................................................... 38 table of contents BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 8 broadcom confidential bluetooth 4.1 features ............................................................................................................................... 39 bluetooth low energy ............................................................................................................................... 39 link control layer ............................................................................................................................... ....... 39 test mode support ............................................................................................................................... ...... 40 bluetooth power management unit .......................................................................................................... 40 rf power management ............................................................................................................ ............ 40 host controller power management ............................................................................................... ...... 40 bbc power management........................................................................................................... ........... 43 wideband speech................................................................................................................ .......... 43 packet loss concealment ........................................................................................................ ..... 43 audio rate-matching algorithms................................................................................................. ... 44 codec encoding................................................................................................................. ............ 44 multiple simultaneous a2dp audio stream................................................................................... 44 fm over bluetooth .............................................................................................................. .................. 44 burst buffer operation ......................................................................................................... .......... 44 adaptive frequency hopping .................................................................................................................... 45 advanced bluetooth/wlan coexistence ................................................................................................. 45 fast connection (interlace d page and inquiry scans) ........................................................................... 45 section 6: microprocessor and memory unit for bluetooth.......................................... 46 ram, rom, and patch memory ................................................................................................................. 46 reset ............................................................................................................................... ............................. 46 section 7: bluetooth peripheral transport unit ............................................................. 47 spi interface ............................................................................................................................... ................. 47 spi/uart transport detection .................................................................................................................. 47 pcm interface ............................................................................................................................... ............... 48 slot mapping ................................................................................................................... ...................... 48 frame synchronization .......................................................................................................... ............... 48 data formatting................................................................................................................ ..................... 48 wideband speech support ........................................................................................................ ........... 49 multiplexed bluetooth over pcm ................................................................................................. ......... 49 burst pcm mode ................................................................................................................. .................. 49 pcm interface timing........................................................................................................... ................. 50 short frame sync, master mode .................................................................................................. .50 short frame sync, slave mode ................................................................................................... .. 51 long frame sync, master mode................................................................................................... .52 long frame sync, slave mode.................................................................................................... .. 53 short frame sync, burst mode................................................................................................... ... 54 long frame sync, burst mode .................................................................................................... .. 55 table of contents BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 9 broadcom confidential uart interface ............................................................................................................................... ............. 56 i 2 s interface ............................................................................................................................... .................. 57 i 2 s timing....................................................................................................................... ....................... 58 section 8: fm receiver subsystem ................................................................................. 60 fm radio ............................................................................................................................... ...................... 60 digital fm audio interfaces ....................................................................................................................... 60 fm over bluetooth ............................................................................................................................... ...... 60 esco ............................................................................................................................... ............................. 60 wideband speech link .............................................................................................................................. 6 1 a2dp ............................................................................................................................... ............................. 61 autotune and search algorithms ............................................................................................................. 61 audio features ............................................................................................................................... ............ 62 rds/rbds ............................................................................................................................... .................... 64 section 9: wlan global functions ................................................................................. 65 wlan cpu and memory subsystem ........................................................................................................ 65 one-time programmable memory ............................................................................................................ 65 gpio interface ............................................................................................................................... .............. 65 external coexistence interface ................................................................................................................. 66 uart interface ............................................................................................................................... ............. 67 jtag/swd interface ............................................................................................................................... .... 67 section 10: wlan host interfaces................................................................................... 68 sdio v3.0 ............................................................................................................................... ...................... 68 sdio pins...................................................................................................................... ........................ 69 pci express interface ............................................................................................................................... .. 70 transaction layer interface.................................................................................................... ............... 71 data link layer ................................................................................................................ ..................... 71 physical layer ................................................................................................................. ...................... 71 logical subblock ............................................................................................................... .................... 71 scrambler/descrambler.......................................................................................................... ............... 71 8b/10b encoder/decoder......................................................................................................... ............. 72 elastic fifo................................................................................................................... ........................ 72 electrical subblock ............................................................................................................ .................... 72 configuration space............................................................................................................ .................. 72 section 11: wireless lan mac and phy ........................................................................ 73 ieee 802.11ac mac ............................................................................................................................... ..... 73 psm............................................................................................................................ ........................... 74 wep ............................................................................................................................ .......................... 75 txe ............................................................................................................................ ........................... 75 table of contents BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 10 broadcom confidential rxe ............................................................................................................................ ........................... 75 ifs............................................................................................................................ ............................. 75 tsf............................................................................................................................ ............................ 76 nav ............................................................................................................................ ........................... 76 mac-phy interface.............................................................................................................. ................. 76 ieee 802.11ac phy ............................................................................................................................... ...... 76 section 12: wlan radio subsystem ............................................................................. 78 receiver path ............................................................................................................................... ............... 78 transmit path ............................................................................................................................... ............... 78 calibration ............................................................................................................................... .................... 78 section 13: ball map and pin descriptions..................................................................... 80 ball map ............................................................................................................................... ........................ 80 pin list by pin number .............................................................................................................................. 8 1 pin list by pin name ............................................................................................................................... ... 83 pin descriptions ............................................................................................................................... .......... 85 wlan gpio signals and strapping options ........................................................................................... 91 multiplexed bluetooth gpio signals ............................................................................................. ........ 92 i/o states ............................................................................................................................... ...................... 94 section 14: dc characteristics ........................................................................................ 97 absolute maximum ratings ...................................................................................................................... 97 environmental ratings .............................................................................................................................. 9 8 electrostatic discharge specifications .................................................................................................... 98 recommended operating conditions and dc characteristics ............................................................. 99 section 15: bluetooth rf specifications ...................................................................... 100 section 16: fm receiver specifications........................................................................ 107 section 17: wlan rf specifications ............................................................................ 112 introduction ............................................................................................................................... ................ 112 2.4 ghz band general rf specifications ............................................................................................... 113 wlan 2.4 ghz receiver performance specifications .......................................................................... 113 wlan 2.4 ghz transmitter performance specifications ..................................................................... 117 wlan 5 ghz receiver performance specifications ............................................................................. 118 wlan 5 ghz transmitter performance specifications ........................................................................ 124 general spurious emissions specifications ......................................................................................... 125 transmitter spurious emissions specifications .................................................................................. 125 2.4 ghz band spurious emissions .............................................................................................. 12 6 20 mhz channel spacing .................................................................................................... 126 5 ghz band spurious emissions ................................................................................................. 12 7 table of contents BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 11 broadcom confidential 20 mhz channel spacing .................................................................................................... 127 40 mhz channel spacing .................................................................................................... 128 80 mhz channel spacing .................................................................................................... 129 receiver spurious emissions specifications ..................................................................................... .129 section 18: internal regulator electrical specifications ............................................. 130 core buck switching regulator .............................................................................................................. 130 3.3v ldo (ldo3p3) ............................................................................................................................... ... 131 2.5v ldo (btldo2p5) ............................................................................................................................. 13 2 cldo ............................................................................................................................... .......................... 133 lnldo ............................................................................................................................... ........................ 134 pcie ldo ............................................................................................................................... .................... 135 section 19: system power consumption...................................................................... 136 wlan current consumption ................................................................................................................... 136 2.4 ghz mode ................................................................................................................... .................. 136 5 ghz mode ..................................................................................................................... ................... 137 bluetooth current consumption ............................................................................................................. 138 section 20: interface timing and ac characteristics .................................................. 139 sdio timing ............................................................................................................................... ............... 139 sdio default mode timing ....................................................................................................... .......... 139 sdio high-speed mode timing.................................................................................................... ...... 141 sdio bus timing specifications in sdr modes ................................................................................. 142 clock timing ................................................................................................................... ............. 142 card input timing.............................................................................................................. ........... 143 card output timing............................................................................................................. ......... 144 sdio bus timing specifications in ddr50 mode............................................................................... 146 data timing.................................................................................................................... .............. 147 pci express interface parameters .......................................................................................................... 148 jtag timing ............................................................................................................................... .............. 150 swd timing ............................................................................................................................... ............... 150 section 21: power-up sequence and timing ............................................................... 151 sequencing of reset and regulator control signals ........................................................................... 151 description of control signals ................................................................................................. ............ 151 control signal timing diagrams................................................................................................. ......... 152 section 22: package information ................................................................................... 154 package thermal characteristics ........................................................................................................... 154 junction temperature estimation and psi jt versus theta jc ........................................................... 154 environmental characteristics ................................................................................................................ 154 table of contents BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 12 broadcom confidential section 23: mechanical information .............................................................................. 155 section 24: ordering information .................................................................................. 157 list of figures BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 13 broadcom confidential list of figures figure 1: functional block diagram.............................................................................................. ..................... 1 figure 2: BCM43455 block diagram ................................................................................................ ............... 20 figure 3: typical power topology (page 1 of 2).................................................................................. ............ 24 figure 4: typical power topology (page 2 of 2).................................................................................. ............ 25 figure 5: recommended oscillator configuration .................................................................................. ......... 29 figure 6: recommended circuit to use with an external reference clock .................................................... 30 figure 7: startup signaling sequence prior to software download ................................................................ 4 2 figure 8: cvsd decoder output waveform without plc .............................................................................. .44 figure 9: cvsd decoder output waveform after applying plc..................................................................... 44 figure 10: functional multiplex data diagram.................................................................................... ............. 49 figure 11: pcm timing diagram (short frame sync, master mode) .............................................................. 50 figure 12: pcm timing diagram (short frame sync, slave mode) ................................................................ 51 figure 13: pcm timing diagram (long frame sync, master mode)............................................................... 52 figure 14: pcm timing diagram (long frame sync, slave mode)................................................................. 53 figure 15: pcm burst mode timing (receive only, short frame sync) ......................................................... 54 figure 16: pcm burst mode timing (receive only, long frame sync) ......................................................... 55 figure 17: uart timing .......................................................................................................... ........................ 57 figure 18: i 2 s transmitter timing ........................................................................................................... ......... 59 figure 19: i 2 s receiver timing.............................................................................................................. .......... 59 figure 20: audio snr for blend, switch, and fme modes........................................................................... ... 62 figure 21: stereo separation for blend, switch, and fme modes .................................................................. 6 3 figure 22: example soft mute characteristic ..................................................................................... ............. 63 figure 23: broadcom gci or bt-sig wci-2 lte coexistence interface ........................................................ 66 figure 24: 3-wire lte coexistence interface..................................................................................... ............. 66 figure 25: signal connections to sdio host (sd 4-bit mode) ...................................................................... .. 69 figure 26: signal connections to sdio host (sd 1-bit mode) ...................................................................... .. 69 figure 27: pci express layer model .............................................................................................. ................. 70 figure 28: wlan mac architecture ................................................................................................ ................ 73 figure 29: wlan phy block diagram............................................................................................... .............. 77 figure 30: radio functional block diagram ....................................................................................... ............. 79 figure 31: 140-ball wlbga map?bottom view (balls facing up) ............................................................... 80 figure 32: port locations for bluetooth testing................................................................................. ............ 100 figure 33: port locations for wlan testing ...................................................................................... ........... 112 figure 34: sdio bus timing (default mode) ....................................................................................... .......... 139 figure 35: sdio bus timing (high-speed mode).................................................................................... ...... 141 list of figures BCM43455 preliminary data sheet broadcom ? november 5, 2015 ? 43455-ds109-r page 14 broadcom confidential figure 36: sdio clock timing (sdr modes) ........................................................................................ ........ 142 figure 37: sdio bus input timing (sdr modes) .................................................................................... ...... 143 figure 38: sdio bus output timing (sdr modes up to 100 mhz) ............................................................... 144 figure 39: sdio bus output timing (sdr modes 100 mhz to 208 mhz)..................................................... 144 figure 40: ? top consideration for variable data window (sdr 104 mode) ................................................ 145 figure 41: sdio clock timing (ddr50 mode) ....................................................................................... ....... 146 figure 42: sdio data timing (ddr50 mode) ........................................................................................ ....... 147 figure 43: swd read and write timing............................................................................................ ............ 150 figure 44: wlan = on, bluetooth = on ............................................................................................ ........... 152 figure 45: wlan = off, bluetooth = off.......................................................................................... .......... 152 figure 46: wlan = on, bluetooth = off ........................................................................................... .......... 153 figure 47: wlan = off, bluetooth = on ........................................................................................... .......... 153 figure 48: 140-ball wlbga package mechanical information ..................................................................... 155 figure 49: 140-balls wlbga keep-out areas for pcb layout?top view with balls facing down ............ 156 list of tables BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 15 list of tables table 1: power-up/power-down/reset control signals.............................................................................. .... 28 table 2: crystal oscillator and external clock?requirements and performance ......................................... 30 table 3: external 32.768 khz sleep clock specifications ......................................................................... ...... 33 table 4: power control pin description .......................................................................................... ................. 41 table 5: spi-to-uart signal mapping ............................................................................................. ............... 47 table 6: pcm interface timing specifications (short frame sync, master mode).......................................... 50 table 7: pcm interface timing specifications (short frame sync, slave mode)............................................ 51 table 8: pcm interface timing specifications (long frame sync, master mode) .......................................... 52 table 9: pcm interface timing specifications (long frame sync, slave mode) ............................................ 53 table 10: pcm burst mode (receive only, short frame sync) ...................................................................... 5 4 table 11: pcm burst mode (receive only, long frame sync) ...................................................................... 55 table 12: example of common baud rates.......................................................................................... .......... 56 table 13: uart timing specifications ............................................................................................ ................ 57 table 14: timing for i 2 s transmitters and receivers ...................................................................................... 58 table 15: 3-wire external coexistence interface ................................................................................. ........... 66 table 16: sdio pin description .................................................................................................. ..................... 69 table 17: wlbga pin list by pin number .......................................................................................... ............ 81 table 18: wlbga pin list by pin name............................................................................................ .............. 83 table 19: signal descriptions ................................................................................................... ....................... 85 table 20: strapping options ..................................................................................................... ....................... 91 table 21: gpio multiplexing matrix .............................................................................................. ................... 92 table 22: multiplexed gpio signals .............................................................................................. .................. 93 table 23: i/o states ............................................................................................................ ............................. 94 table 24: absolute maximum ratings .............................................................................................. ............... 97 table 25: environmental ratings ................................................................................................. .................... 98 table 26: esd specifications .................................................................................................... ...................... 98 table 27: recommended operating conditions and dc characteristics ........................................................ 99 table 28: bluetooth receiver rf specifications.................................................................................. .......... 101 table 29: bluetooth transmitter rf specifications.............................................................................. ......... 104 table 30: local oscillator performance.......................................................................................... ............... 106 table 31: ble rf specifications ................................................................................................. .................. 106 table 32: fm receiver specifications ............................................................................................ ............... 107 table 33: 2.4 ghz band general rf specifications................................................................................ ...... 113 table 34: wlan 2.4 ghz receiver performance specifications .................................................................. 113 table 35: wlan 2.4 ghz transmitter performance specifications .............................................................. 117 list of tables BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 16 table 36: wlan 5 ghz receiver performance specifications ..................................................................... 118 table 37: wlan 5 ghz transmitter performance specifications ................................................................. 124 table 38: recommended spectrum analyzer settings ................................................................................ .125 table 39: 2.4 ghz band, 20 mhz channel spacing tx spurious emissions specifications ........................ 126 table 40: 5 ghz band, 20 mhz channel spacing tx spurious emissions specifications ........................... 127 table 41: 5 ghz band, 40 mhz channel spacing tx spurious emissions specifications ........................... 128 table 42: 5 ghz band, 80 mhz channel spacing tx spurious emissions specifications ........................... 129 table 43: 2g and 5g general receiver spurious emissions ........................................................................ 1 29 table 44: core buck switching regulator (cbuck) specifications .............................................................. 130 table 45: ldo3p3 specifications ................................................................................................. ................. 131 table 46: btldo2p5 specifications ............................................................................................... .............. 132 table 47: cldo specifications ................................................................................................... ................... 133 table 48: lnldo specifications .................................................................................................. .................. 134 table 49: pcie ldo specifications ............................................................................................... ................ 135 table 50: 2.4 ghz mode wlan power consumption ................................................................................... 136 table 51: 5 ghz mode wlan power consumption ..................................................................................... .137 table 52: bluetooth and ble current consumption................................................................................. ..... 138 table 53: sdio bus timing parameters (default mode)............................................................................. .. 139 table 54: sdio bus timing parameters (high-speed mode)....................................................................... 141 table 55: sdio bus clock timing parameters (sdr modes) ....................................................................... 142 table 56: sdio bus input timing parameters (sdr modes) ........................................................................ 14 3 table 57: sdio bus output timing parameters (sdr modes up to 100 mhz)............................................. 144 table 58: sdio bus output timing parameters (sdr modes 100 mhz to 208 mhz) .................................. 145 table 59: sdio bus clock timing parameters (ddr50 mode) .................................................................... 146 table 60: sdio bus timing parameters (ddr50 mode) .............................................................................. 1 47 table 61: pci express interface parameters ...................................................................................... .......... 148 table 62: jtag timing characteristics ........................................................................................... .............. 150 table 63: swd read and write timing parameters .................................................................................. ... 150 table 64: package thermal characteristics ....................................................................................... ........... 154 table 65: part ordering information ............................................................................................. ................. 157 about this document broadcom ? november 5, 2015 ? 43455-ds109-r page 17 BCM43455 preliminary data sheet broadcom confidential about this document purpose and audience this data sheet provides details on the functional, operational, and electrical characteristics for the broadcom ? BCM43455. it is intended for hardware design, application, and oem engineers. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . document conventions the following conventions may be used in this document: references the references in this section may be used in conjunction with this document. for broadcom documents, replace the ?xx? in the document number with the largest number available in the repository to ensure that you have the most current version of the document. convention description bold user input and actions: for example, type exit , click ok, press alt+c monospace code: #include command line commands and parameters: wl [-l] |
technical support broadcom ? november 5, 2015 ? 43455-ds109-r page 18 BCM43455 preliminary data sheet broadcom confidential technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads & support site ( http://www.broadcom.com/support/ ). BCM43455 overview BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 19 section 1: BCM43455 overview overview the broadcom BCM43455 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated ieee 802.1 a/b/g/n/ac mac/baseband/radio, bluetooth 4.1 + edr (enhanced data rate), and fm receiver. it provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 2 on page 20 shows the interconnect of all the major physical blocks in the BCM43455 and their associated external interfaces, which are described in greater detail in the following sections. overview BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 20 figure 2: BCM43455 block diagram wlan btfm rx/tx lcu ble apu bluerf uart pcm i 2 s usb port control gpio timers wd pause ahb2apb registers dma jtag master ahb bus matrix ram rom armcm3 wlan master slave fm rx modem bt rf nic-301 axi backplane tcm ram 800 kb rom 704 kb axi2anb ahb2axi wlan bt access wlan ram sharing armcr4 chip common (otp) axi2apb pcie sdiod dot11mac (d11) gci coex i/f 11 ieee 802.11ac phy (rev. 4) shared lna control and other coex i/f 2.4 ghz/5 ghz tiny radio wl_host_wake uart wl_dev_wkae jtag other gpios sdio 3.0 pcie rf switch controls xtal fm analog audio 32 khz external lpo bt_host_wake bt_dev_wake uart usb 1.1 pcm i 2 s other gpios pmu vbat wl_reg_on bt_reg_on gci seci uart and gci gpios bt pa clb shared 2.4 lna 2.4 ghz pa wlan: 5 ghz: ipa, ilna, elg, etr 2 ghz: ipa, ilna, elg, itr bt: shared lna, itr etr 5 ghz pa lna l l diplexer lna 5 ghz pa driver standards compliance BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 21 standards compliance the BCM43455 supports the following standards: ? bluetooth 2.1 + edr ? bluetooth 3.0 ? bluetooth 4.1 (bluetooth low energy) ? ieee 802.11ac single-stream mandatory and optional requirements for 20, 40, and 80 mhz channels ? ieee 802.11n (handheld device class, section 11) ? ieee 802.11a ? ieee 802.11b ? ieee 802.11g ? ieee 802.11d ? ieee 802.11h ? ieee 802.11i ? security: ?wep ? wpa personal ? wpa2 personal ?wmm ? wmm-ps (u-apsd) ?wmm-sa ? aes (hardware accelerator) ? tkip (hardware accelerator) ? ckip (software support) ? proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ?wfaec ? ieee 802.15.2 coexistence compliance (on-silicon solution compliant with ieee 3-wire requirements) the BCM43455 supports the following future drafts/standards: ? ieee 802.11r (fast roaming between aps) ? ieee 802.11w (secure management frames) mobile phone usage model BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 22 ? ieee 802.11 extensions: ? ieee 802.11e qos enhancements (as per the wmm specification is already supported) ? ieee 802.11h 5 ghz extensions ? ieee 802.11i mac enhancements ? ieee 802.11k radio resource measurement mobile phone usage model the BCM43455 incorporates a number of unique features to simplify integration into mobile phone platforms. its flexible pcm and uart interfaces enable it to transparently connect with the existing circuits. in addition, the tcxo and lpo inputs allow the use of existing handset features to further minimize the size, power, and cost of the complete system. ? the pcm interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices. ? the uart interface supports hardware flow control with tight integration to power control sideband signaling to support the lowest power operation. ? the crystal oscillator interface accommodates any of the typical reference frequencies used by cell phones. ? fm digital interfaces can use either i 2 s or pcm. ? the highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions output regardless of the state of operation. it has been fully characterized in the global cellular bands. ? the transceiver design has excellent blocking and intermodulation performance in the presence of a cellular transmission (lte, gsm, gprs, cdma, wcdma, or iden). the BCM43455 is designed to directly interface with new and existing handset designs. power supplies and power management BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 23 section 2: power supplies and power management power supply topology one buck regulator, multiple ldo regulators, and a power management unit (pmu) are integrated into the BCM43455. all regulators are programmable via the pmu. these blocks simplify power supply design for bluetooth, and wlan functions in embedded designs. a single vbat (3.0v to 5.25v dc max.) and vio supply (1.8v to 3.3v) can be used, with all additional voltages being provided by the regulators in the BCM43455. two control signals, bt_reg_on and wl_reg_on, are used to power-up the regulators and take the respective section out of reset. the cbuck cldo and lnldo power-up when any of the reset signals are deasserted. all regulators are powered down only when both bt_reg_on and wl_reg_on are deasserted. the cldo and lnldo may be turned off/on based on the dynamic demands of the digital baseband. the BCM43455 allows for an extremely low power-consumption mode by completely shutting down the cbuck, cldo, and lnldo regulators. when in this state, the lpldo1 (which is the low-power linear regulator that is supplied by the system vio supply) provides the BCM43455 with all required voltage, further reducing leakage currents. BCM43455 pmu features ? vbat to 1.35vout (170 ma nominal, 600 ma maximum) core-buck (cbuck) switching regulator ? vbat to 3.3vout (200 ma nominal, 450 ma?850 ma maximum) ldo3p3 ? vbat to 2.5vout (15 ma nominal, 70 ma maximum) btldo2p5 ? 1.35v to 1.2vout (100 ma nominal, 150 ma maximum) lnldo ? 1.35v to 1.2vout (80 ma nominal, 200 ma maximum) cldo with bypass mode for deep-sleep ? 1.35v to 1.2vout (35 ma nominal, 55 ma maximum) ldo for pcie ? additional internal ldos (not externally accessible) ? pmu internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. broadcom ? november 5, 2015 ? 43455-ds109-r page 24 BCM43455 pmu features broadcom confidential BCM43455 preliminary data sheet figure 3 and figure 4 on page 25 show the regulators and a typical power topology. figure 3: typical power topology (page 1 of 2) wlan/bt/clb/top, always on wl subcore bt digital wl rf ? xtal bt rf lnldo 100 ma internal lnldo 10 ma internal vcoldo 80 ma internal lnldo 80 ma internal lnldo 80 ma wl rf - logen wl rf ? lna wl rf ? afe and tia wl rf ? tx core buck regulator cbuck max 600 ma avg 170 ma lpldo1 3 ma vbat vddio 1.1v 1.35v 1.3v- 1.2v- 0.95v (avs) 1.2v 1.2v 1.2v 1.2v 2.2 h 0806 0603 4.7 f 0402 4.7 f 0402 2.2 f 0402 1.2v wl rf ? rfpll pfd and mmd xtal ldo 30 ma 1.2v 1 f 0402 pcie pll, rxtx wl_reg_on bt_reg_on wl bbpll/dfll wl vddm (srams + aos) wl phy wl otp bt vddm cldo max 200 ma avg 80 ma (bypass in deep sleep) pcie ldo max 55 ma avg 35 ma (bypass/off in deepsleep) 0.47 f 0201 1.2v internal lnldo 10 ma wl rf ? adc ref 1.2v wl rf - tx mixer and pa (not all versions) gnd 0.1 f 0201 shaded areas are internal to the device. no power switch power switch BCM43455 broadcom ? november 5, 2015 ? 43455-ds109-r page 25 BCM43455 pmu features broadcom confidential BCM43455 preliminary data sheet figure 4: typical power topology (page 2 of 2) 2.5v internal lnldo 8 ma wl rf ? cp btldo2p5 max 70 ma avg 15 ma bt class 1 pa ldo3p3 spike 800 ma max 450 ma avg 200 ma wl rf ? pad (2.4 ghz, 5 ghz) wl otp 3.3v vddio_rf vbat 3.3v 4.7 f 0402 2.5v wl rf ? pa (2.4 ghz, 5 ghz) wl rf ? vco 2.5v internal lnldo 25 ma 2.5v 2.2 f 0402 2.5v internal lnldo 10 ma wl rf ? rx, tx, nmos minipmu ldos 2.5v 10 pf 0201 2.5v shaded areas are internal to the device. no power switch power switch no dedicated power switch, but internal power-down modes and block-specific power switches. BCM43455 wlan power management BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 26 wlan power management the BCM43455 has been designed with the stringent power consumption requirements of mobile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. additionally, the BCM43455 integrated ram is a high vt memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the BCM43455 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides significant power savings by putting the BCM43455 into various power management states appropriate to the current environment and activities that are being performed. the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-up sequences are fully programmable. configurable, free- running counters (running at 32.768 khz lpo clock) in the pmu sequencer are used to turn on/turn off individual regulators and power switches. clock speeds are dynamically changed (or gated altogether) for the current mode. slower clock speeds are used wherever possible. the BCM43455 wlan power states are described as follows: ? active mode? all wlan blocks in the BCM43455 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. ? doze mode?the radio, analog domains, and most of the linear regulators are powered down. the rest of the BCM43455 remains powered up in an idle state. all main clocks (pll, crystal oscillator or tcxo) are shut down to reduce active power to the minimum. the 32.768 khz lpo clock is available only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake-up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. ? deep-sleep mode?most of the chip including both analog and digital domains and most of the regulators are powered off. logic states in the digital core are saved and preserved into a retention memory in the always-on domain before the digital core is powered off. upon a wake-up event triggered by the pmu timers, an external interrupt or a host resume through the pcie bus, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy hw reinitialization. ? power-down mode?the BCM43455 is effectively powered off by shutting down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. pmu sequencing the pmu sequencer is used to minimize system power consumption. it enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. resource requests may derive from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource request timers. the pmu sequencer maps clock requests into a set of resources required to produce the requested clocks. power-off shutdown BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 27 each resource is in one of four states: ? enabled ?disabled ? transition_on ? transition_off the timer contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can transition immediately from disabled to enabled. similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, the pmu sequencer performs the following actions: ? computes the required resource set based on requests and the resource dependency table. ? decrements all timers whose values are non zero. if a timer reaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. ? compares the request with the current resource status and determines which resources must be enabled or disabled. ? initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents. ? initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. power-off shutdown the BCM43455 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. when the BCM43455 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the BCM43455 to be effectively off while keeping the i/o pins powered so that they do not draw extra current from any other devices connected to the i/o. during a low-power shutdown state, provided vddio remains applied to the BCM43455, all outputs are tristated, and most inputs signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM43455 to be fully integrated in an embedded device and take full advantage of the lowest power-savings modes. when the BCM43455 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down. power-up/power-down/reset circuits BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 28 power-up/power-down/reset circuits the BCM43455 has two signals (see table 1 ) that enable or disable the bluetooth and wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagrams of these signals and the required power-up sequences, see section 21: ?power-up sequence and timing,? on page 151 . table 1: power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu (with bt_reg_on) to power-up the wlan section. it is also or-gated with the bt_reg_on input to control the internal BCM43455 regulators. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if bt_reg_on and wl_reg_on are both low, the regulators are disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on this signal is used by the pmu (with wl_reg_on) to decide whether or not to power down the internal BCM43455 regulators. if bt_reg_on and wl_reg_on are low, the regulators will be disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. frequency references BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 29 section 3: frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference may be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. crystal interface and clock generation the BCM43455 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscillator including all external components is shown in figure 5 . consult the reference schematics for the latest configuration. figure 5: recommended os cillator configuration a fractional-n synthesizer in the BCM43455 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. the recommended default frequency reference is a 37.4 mhz crystal. the signal characteristics for the crystal interface are listed in table 2 on page 30 . note: although the fractional-n synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. contact broadcom for further details. wrf_xtal_xon wrf_xtal_xop c c 37.4 mhz x ohms 27 pf 27 pf note: a reference schematic is available for further details. contact your broadcom fae. external frequency reference BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 30 external frequency reference as an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise requirements listed in ta b l e 2 . if used, the external clock should be connected to the wrf_xtal_xop pin through an external 1000 pf coupling capacitor, as shown in figure 6 . the internal clock buffer connected to this pin will be turned off when the BCM43455 goes into sleep mode. when the clock buffer turns on and off there will be a small impedance variation. power must be supplied to the wrf_xtal_vdd1p35 pin. figure 6: recommended circuit to use with an external reference clock table 2: crystal oscillator and extern al clock?requirements and performance parameter conditions/notes crystal a external frequency reference b c min. typ. max. min. typ. max. units frequency 2.4g and 5g bands, ieee 802.11ac operation 35 ? 52 ? 52 ? mhz frequency 5g band, ieee 802.11n operation only 19? 5235? 52mhz 2.4g band ieee 802.11n operation, and both bands legacy ieee 802.11a/b/g operation only between 19 mhz and 52 mhz d, e frequency tolerance over the lifetime of the equipment, including temperature f without trimming ?20 ? 20 ?20 ? 20 ppm crystal load capacitance ? ?16????pf esr ? ??60??? ? drive level external crystal must be able to tolerate this drive level. 200????? w input impedance (wrf_xtal_xop) resistive ? ? ? 30k 100k ? ? capacitive ??7.5??7.5pf wrf_xtal_xop input low level dc-coupled digital signal ???0?0.2v reference clock nc 1000 pf wrf_xtal_xop wrf_xtal_xon external frequency reference BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 31 wrf_xtal_xop input high level dc-coupled digital signal ???1.0?1.26v wrf_xtal_xop input voltage (see figure 6 on page 30 ) ieee 802.11a/b/g operation only ? ? ? 400 ? 1200 mv p-p wrf_xtal_xop input voltage (see figure 6 on page 30 ) ieee 802.11n/ac ac-coupled analog input ???1??v p-p duty cycle 37.4 mhz clock ???405060% phase noise g (ieee 802.11b/g) 37.4 mhz clock at 10 khz offset??????129dbc/hz 37.4 mhz clock at 100 khz offset??????136dbc/hz phase noise g (ieee 802.11a) 37.4 mhz clock at 10 khz offset??????137dbc/hz 37.4 mhz clock at 100 khz offset??????144dbc/hz phase noise g (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset??????134dbc/hz 37.4 mhz clock at 100 khz offset??????141dbc/hz phase noise g (ieee 802.11n, 5ghz) 37.4 mhz clock at 10 khz offset??????142dbc/hz 37.4 mhz clock at 100 khz offset??????149dbc/hz phase noise g (ieee 802.11ac, 5ghz) 37.4 mhz clock at 10 khz offset??????148dbc/hz 37.4 mhz clock at 100 khz offset??????155dbc/hz a. (crystal) use wrf_xtal_xon and wrf_xtal_xop. b. see ?external frequency reference? on page 30 for alternative connection methods. c. for a clock reference other than 37.4 mhz, 20 log10(f/ 37.4) db should be added to the limits, where f = the reference clock frequency in mhz. d. bt_tm6 should be tied low for a 52 mhz clock reference. for other frequencies, bt_tm6 should be tied high. note that 52 mhz is not an auto-detected frequency using the lpo clock. e. the frequency step size is approximately 80 hz resolution. f. it is the responsibility of the equipment designer to select oscillator components that comply with these specifications. g. assumes that external clock has a flat phase noise response above 100 khz. table 2: crystal oscillator and external clock?requirements and performance (cont.) parameter conditions/notes crystal a external frequency reference b c min. typ. max. min. typ. max. units frequency selection BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 32 frequency selection any frequency within the ranges specified for the crystal and tcxo reference may be used. these include not only the standard handset reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, 38.4, and 52 mhz, but also other frequencies in this range, with approximately 80 hz resolution. the BCM43455 must have the reference frequency set correctly in order for any of the uart or pcm interfaces to function correctly, since all bit timing is derived from the reference frequency. the reference frequency for the BCM43455 may be set in the following ways: ?set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. ? auto-detect any of the standard handset reference frequencies using an external lpo clock. for applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard frequencies commonly used, the BCM43455 automatically detects the reference frequency and programs itself to the correct reference frequency. in order for auto frequency detection to work correctly, the BCM43455 must have a valid and stable 32.768 khz lpo clock that meets the requirements listed in table 3 on page 33 and is present during power-on reset. note: the fractional-n synthesizer can support many reference frequencies. however, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. contact broadcom for further details. external 32.768 khz low-power oscillator BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 33 external 32.768 khz low-power oscillator the BCM43455 uses a secondary low frequency clock for low-power-mode timing. either the internal low- precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over process, voltage, and temperature, which is adequate for some applications. however, one trade-off caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake-up earlier to avoid missing beacons. whenever possible, the preferred approach is to use a precision external 32.768 khz clock that meets the requirements listed in ta b le 3 . table 3: external 32.768 khz sleep clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?3300 mv, p-p signal type square-wave or sine-wave ? input impedance a a. when power is applied or switched off. >100k <5 ? pf clock jitter (during initial start-up) <10,000 ppm bluetooth and fm subsystem overview BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 34 section 4: bluetooth and fm subsystem overview the BCM43455 is a bluetooth 4.1 + edr-compliant, baseband processor with 2.4 ghz transceiver with an integrated fm/rds/rbds receiver. it features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a bluetooth plus fm radio solution. the BCM43455 is the optimal solution for any bluetooth voice and/or data application that also requires an fm radio receiver. the bluetooth subsystem presents a standard host controller interface (hci) via a high-speed uart and pcm for audio. the fm subsystem supports the hci control interface, analog output, as well as i 2 s and pcm interfaces. the BCM43455 incorporates all bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume. the BCM43455 bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices. it provides full radio compatibility to operate simultaneously with gps, wlan, and cellular radios. the bluetooth transmitter also features a class 1 power amplifier with class 2 capability. features primary BCM43455 bluetooth features include: ? supports key features of upcoming bluetooth standards ? fully supports bluetooth core specification version 4.1 + edr features: ? adaptive frequency hopping (afh) ? quality of service (qos) ? extended synchronous connections (esco)?voice connections ? fast connect (interlaced page and inquiry scans) ? secure simple pairing (ssp) ? sniff subrating (ssr) ? encryption pause resume (epr) ? extended inquiry response (eir) ? link supervision timeout (lst) ? uart baud rates up to 4 mbps ? supports all bluetooth 4.1 + hs packet types ? supports maximum bluetooth data rates over hci uart ? multipoint operation with up to seven active slaves ? maximum of seven simultaneous active acl links ? maximum of three simultaneous active sco and esco connections with scatternet support features BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 35 ? trigger broadcom fast connect (tbfc) ? narrowband and wideband packet loss concealment ? scatternet operation with up to four active piconets with background scan and support for scatter mode ? high-speed hci uart transport support with low-power out-of-band bt_dev_wake and bt_host_wake signaling (see ?host controller power management? on page 40 ) ? channel quality driven data rate and packet type selection ? standard bluetooth test modes ? extended radio and production test mode features ? full support for power savings modes ? bluetooth clock request ? bluetooth standard sniff ? deep-sleep modes and software regulator shutdown ? supports a low-power crystal, which can be used during power save mode for better timing accuracy. major fm radio features include: ? 65 mhz to 108 mhz fm bands supported (us, europe, and japan) ? fm subsystem control using the bluetooth hci interface ? fm subsystem operates from reference clock inputs. ? improved audio interface capabilities with full-featured bidirectional pcm and i 2 s ?i 2 s can be master or slave. fm receiver-specific features include: ? excellent fm radio performance with 1 v sensitivity for 26 db (s + n) n ? signal-dependent stereo/mono blending ? signal dependent soft mute ? auto search and tuning modes ? audio silence detection ? rssi, if frequency, status indicators ? rds and rbds demodulator and decoder with filter and buffering functions ? automatic frequency jump bluetooth radio BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 36 bluetooth radio the BCM43455 has an integrated radio transceiver that has been optimized for use in 2.4 ghz bluetooth wireless systems. it has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. it is fully compliant with the bluetooth radio specification and edr specification and meets or exceeds the requirements to provide the highest communication link quality of service. transmit the BCM43455 features a fully integrated zero-if transmitter. the baseband transmit data is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path consists of signal filtering, i/q upconversion, output power amplifier, and rf filtering. the transmitter path also incorporates ? /4-dqpsk for 2 mbps and 8-dpsk for 3 mbps to support edr. the transmitter section is compatible to the bluetooth low energy specification. the transmitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. digital modulator the digital modulator performs the data modulation and filtering required for the gfsk, ? /4-dqpsk, and 8-dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct vco modulation schemes. digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit-synchronization algorithm. power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature-compensated design. this provides greater flexibility in front-end matching and filtering. due to the linear nature of the pa combined with some integrated filtering, external filtering is required to meet the bluetooth and regulatory harmonic and spurious requirements. for integrated mobile handset applications in which bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. the transmitter features a sophisticated on-chip transmit signal strength indicator (tssi) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. bluetooth radio BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 37 receiver the receiver path uses a low-if scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology with built-in out-of-band attenuation enables the BCM43455 to be used in most applications with minimal off-chip filtering. for integrated handset operation, in which the bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. receiver signal strength indicator the radio portion of the BCM43455 provides a receiver signal strength indicator (rssi) signal to the baseband, so that the controller can take part in a bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. local oscillator generation a local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immunity to lo pulling during pa operation. the BCM43455 uses an internal rf and if loop filter. calibration the BCM43455 radio transceiver features an automated calibration scheme that is fully self contained in the radio. no user interaction is required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the performance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. this takes into account process variation and temperature variation. calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and heats during normal operation in its environment. bluetooth baseband core BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 38 section 5: bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time critical functions required for high-performance bluetooth operation. the bbc manages the buffering, segmentation, and routing of data for all connections. it also buffers data that passes through it, handles data flow control, schedules sco/acl tx/rx transactions, monitors bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes hci packets. in addition to these functions, it independently handles hci event types, and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of the tx/rx data before sending over the air: ? symbol timing recovery, data deframing, forward error correction (fec), header error control (hec), cyclic redundancy check (crc), data decryption, and data dewhitening in the receiver. ? data framing, fec generation, hec generation, crc generation, key generation, data encryption, and data whitening in the transmitter. bluetooth 4.0 features the bbc supports all bluetooth 4.0 features, with the following benefits: ? dual-mode bluetooth low energy (bt and ble operation) ? extended inquiry response (eir): shortens the time to retrieve the device name, specific profile, and operating mode. ? encryption pause resume (epr): enables the use of bluetooth technology in a much more secure environment. ? sniff subrating (ssr): optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. ? secure simple pairing (ssp): reduces the number of steps for connecting two devices, with minimal or no user interaction required. ? link supervision time out (lsto): additional commands added to hci and link management protocol (lmp) for improved link time-out supervision. ? qos enhancements: changes to data traffic control, which results in better link performance. audio, human interface device (hid), bulk traffic, sco, and enhanced sco (esco) are improved with the erroneous data (ed) and packet boundary flag (pbf) enhancements. bluetooth 4.1 features BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 39 bluetooth 4.1 features the bbc supports all bluetooth 4.1 features, with the following benefits: ? dual-mode classic bluetooth and classic low energy (bt and ble) operation ? low-energy physical layer ? low-energy link layer ? enhancements to hci for low energy ? low-energy direct test mode ? 128 aes-ccm secure connection for both bt and ble bluetooth low energy the BCM43455 supports the bluetooth low energy operating mode. link control layer the link control layer is part of the bluetooth link control functions that are implemented in dedicated logic in the link control unit (lcu). this layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. each task performs a different state in the bluetooth link controller. ? major states: ? standby ? connection ? substates: ?page ? page scan ? inquiry ? inquiry scan ?sniff note: the BCM43455 is compatible with the bluetooth low energy operating mode, which provides a dramatic reduction in the power consumption of the bluetooth radio and baseband. the primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls. test mode support BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 40 test mode support the BCM43455 fully supports bluetooth test mode as described in part i:1 of the specification of the bluetooth system version 3.0 . this includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the BCM43455 also supports enhanced testing features to simplify rf debugging and qualification and type-approval testing. these features include: ? fixed frequency carrier wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis ? fixed frequency constant receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissions testing for receive mode ? fixed frequency constant transmission ? 8-bit fixed pattern or prbs-9 ? enables modulated signal measurements with standard rf test equipment bluetooth power management unit the bluetooth power management unit (pmu) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. the power management functions provided by the BCM43455 are: ? rf power management ? host controller power management ? ?bbc power management? on page 43 ? ?fm over bluetooth? on page 44 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz transceiver. the transceiver then processes the power-down functions accordingly. host controller power management when running in uart mode, the BCM43455 may be configured so that dedicated signals are used for power management hand-shaking between the BCM43455 and the host. the basic power saving functions supported by those hand-shaking signals include the standard bluetooth defined power savings modes and standby modes of operation. table 4 on page 41 describes the power-control handshake signals used with the uart interface. bluetooth power management unit BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 41 note: pad function control register is set to 0 for these pins. see ?dc characteristics? on page 97 for more details. table 4: power control pin description signal mapped to pin type description bt_dev_wake bt_gpio_0 i bluetooth device wake-up: signal from the host to the BCM43455 indicating that the host requires attention. ? asserted: the bluetooth device must wake-up or remain awake. ? deasserted: the bluetooth device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. bt_host_wake bt_gpio_1 o host wake-up. signal from the BCM43455 to the host indicating that the BCM43455 requires attention. ? asserted: host device must wake-up or remain awake. ? deasserted: host device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. bt_clk_req bt_clk_req_out wl_clk_req_out o the BCM43455 asserts bt_clk_req when bluetooth or wlan wants the host to turn on the reference clock. the bt_clk_req polarity is active-high. add an external 100 k ? pull-down resistor to ensure the signal is deasserted when the BCM43455 powers up or resets when vddio is present. bluetooth power management unit BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 42 figure 7 shows the startup signaling sequence prior to software download. figure 7: startup signaling sequence prior to software download hostresetx vddio lpo bt_dev_wake bt_uart_cts_n clk_req_out bt_host_wake bt_reg_on bt_uart_rts_n host ios configured host ios unconfigured bth ios configured bth ios unconfigured t4 t5 t3 t2 t1 notes : t1 is the time for host to settle it?s ios after a reset. t2 is the time for host to drive bt_reg_on high after the host ios are configured. t3 is the time for bth (bluetooth) device to settle its ios after a reset and reference clock settling time has elapsed. t4 is the time for bth device to drive bt_uart_rts_n low after the host drives bt_uart_cts_n low. this assumes the bth device has already completed initialization. t5 is the time for bth device to drive clk_req_out high after bt_reg_on goes high. note this pin is used for designs that use a n external reference clock source from the host. this pin is irrelevant for crystal reference clock based designs where the bth device generates it? s own reference clock from an external crystal connected to it?s oscillator circuit. timing diagram assumes vbat is present. driven pulled bth device drives this line low indicating transport is ready host side drives this line low bluetooth power management unit BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 43 bbc power management the following are low-power operations for the bbc: ? physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. ? bluetooth-specified low-power connection modes: sniff, hold, and park. while in these modes, the BCM43455 runs on the low-power oscillator and wakes up after a predefined time period. ? a low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. when the BCM43455 is not needed in the system, the rf and core supplies are shut down while the i/o remains powered. this allows the BCM43455 to effectively be off while keeping the i/o pins powered so they do not draw extra current from any other devices connected to the i/o. during the low-power shutdown state, provided vddio remains applied to the BCM43455, all outputs are tristated, and most input signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent current paths or create loading on any digital signals in the system and enables the BCM43455 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. two BCM43455 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have vddio power supplied to it: the frequency reference input (wrf_tcxo_in) and the 32.768 khz input (lpo). when the BCM43455 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. wideband speech the BCM43455 provides support for wideband speech (wbs) using on-chip broadcom smartaudio ? technology. the BCM43455 can perform subband-codec (sbc), as well as msbc, encoding and decoding of linear 16 bits at 16 khz (256 kbps rate) transferred over the pcm bus. packet loss concealment packet loss concealment (plc) improves apparent audio quality for systems with marginal link performance. bluetooth messages are sent in packets. when a packet is lost, it creates a gap in the received audio bit-stream. packet loss can be mitigated in several ways: ? fill in zeros. ? ramp down the output audio signal toward zero (this is the method used in current bluetooth headsets). ? repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). these techniques cause distortion and popping in the audio stream. the BCM43455 uses a proprietary waveform extension algorithm to provide dramatic improvement in the audio quality. figure 8 and figure 9 on page 44 show audio waveforms with and without packet loss concealment. broadcom plc/bec algorithms also support wideband speech. bluetooth power management unit BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 44 figure 8: cvsd decoder output waveform without plc figure 9: cvsd decoder output waveform after applying plc audio rate-matching algorithms the BCM43455 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio stream jitter that may be present when the rate of audio data coming from the host is not the same as the bluetooth audio data rates. codec encoding the BCM43455 can support sbc and msbc encoding and decoding for wideband speech. multiple simultaneous a2dp audio stream the BCM43455 has the ability to take a single audio stream and output it to multiple bluetooth devices simultaneously. this allows a user to share his or her music (or any audio stream) with a friend. fm over bluetooth fm over bluetooth enables the BCM43455 to stream data from fm over bluetooth without requiring the host to be awake. this can significantly extend battery life for usage cases where someone is listening to fm radio on a bluetooth headset. burst buffer operation the BCM43455 has a data buffer that can buffer data being sent over the hci and audio transports, then send the data at an increased rate. this mode of operation allows the host to sleep for the maximum amount of time, dramatically reducing system current consumption. packet loss causes ramp-down adaptive frequency hopping BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 45 adaptive frequency hopping the BCM43455 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. the link quality is determined using both rf and baseband signal processing to provide a more accurate frequency-hop map. advanced bluetoot h/wlan coexistence the BCM43455 includes advanced coexistence technologies that are only possible with a bluetooth/wlan integrated die solution. these coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including applications such as vowlan + sco and video-over-wlan + high fidelity bt stereo. support is provided for platforms that share a single antenna between bluetooth and wlan. dual-antenna applications are also supported. the BCM43455 radio architecture allows for lossless simultaneous bluetooth and wlan reception for shared antenna applications. this is possible only via an integrated solution (shared lna and joint agc algorithm). it has superior performance versus implementations that need to arbitrate between bluetooth and wlan reception. the BCM43455 integrated solution enables mac-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. information is exchanged between the bluetooth and wlan cores without host processor involvement. the BCM43455 also supports transmit power control on the sta together with standard bluetooth tpc to limit mutual interference and receiver desensitization. preemption mechanisms are utilized to prevent ap transmissions from colliding with bluetooth frames. improved channel classification techniques have been implemented in bluetooth for faster and more accurate detection and elimination of interferers (including non- wlan 2.4 ghz interference). the bluetooth afh classification is also enhanced by the wlan core?s channel information. fast connection (interlaced page and inquiry scans) the BCM43455 supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection times. these scanning modes are compatible with the bluetooth version 2.1 page and inquiry procedures. microprocessor and memory unit for bluetooth BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 46 section 6: microprocessor and memory unit for bluetooth the bluetooth microprocessor core is based on the arm cortex-m3 32-bit risc processor with embedded ice- rt debug and jtag interface units. it runs software from the link control (lc) layer, up to the host controller interface (hci). the arm core is paired with a memory unit that contains 845 kb of rom memory for program storage and boot rom, 270 kb of ram for data scratchpad and patch ram code. the internal rom allows for flexibility during power-on reset to enable the same device to be used in various configurations. at power-up, the lower-layer protocol stack is executed from the internal rom memory. external patches may be applied to the rom-based firmware to provide flexibility for bug fixes or features additions. these patches may be downloaded from the host to the BCM43455 through the uart transports. the mechanism for downloading via uart is identical to the proven interface of the bcm4329 and bcm4330 devices. ram, rom, and patch memory the BCM43455 bluetooth core has 270 kb of internal ram which is mapped between general purpose scratch pad memory and patch memory and 845 kb of rom used for the lower-layer protocol stack, test mode software, and boot rom. the patch memory capability enables the addition of code changes for purposes of feature additions and bug fixes to the rom memory. reset the BCM43455 has an integrated power-on reset circuit that resets all circuits to a known power-on state. the bt power-on reset (por) circuit is out of reset after bt_reg_on goes high. if bt_reg_on is low, then the por circuit is held in reset. bluetooth peripheral transport unit BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 47 section 7: bluetooth peripheral transport unit spi interface the BCM43455 supports a slave spi hci transport with an input clock range of up to 16 mhz. higher clock rates can be possible. the physical interface between the spi master and the BCM43455 consists of the four spi signals (spi_csb, spi_clk, spi_si, and spi_so) and one interrupt signal (spi_int). the spi signals are muxed onto the uart signals (see ta b le 5 ). the BCM43455 can be configured to accept active-low or active- high polarity on the spi_csb chip select signal. it can also be configured to drive an active-low or active-high spi_int interrupt signal. bit ordering on the spi_si and spi_so data lines can be configured as either little- endian or big-endian. additionally, proprietary sleep mode and half-duplex handshaking is implemented between the spi master and the BCM43455. the spi_int is required to negotiate the start of a transaction. the spi interface does not require flow control in the middle of a payload. the fifo is large enough to handle the largest packet size. only the spi master can stop the flow of bytes on the data lines, since it controls spi_csb and spi_clk. flow control should be implemented in the higher layer protocols. spi/uart transport detection the bt_host_wake (bt_gpio1) pin is also used for bt transport detection. the transport detection occurs during the power-up sequence. it selects either uart or spi transport operation based on the following pin state: ? if the bt_host_wake (bt_gpio1) pin is pulled low by an external pull-down during power-up, it selects the spi transport interface. ? if the bt_host_wake (bt_gpio1) pin is not pulled low externally during power-up, then the default internal pull-up is detected as a high and it selects the uart transport interface. table 5: spi-to-uart signal mapping spi signals uart signals spi_clk bt_uart_cts_n spi_csb bt_uart_rts_n spi_miso bt_uart_rxd spi_mosi bt_uart_txd spi_int bt_host_wake pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 48 pcm interface the BCM43455 supports two independent pcm interfaces that share the pins with the i2s interfaces. the pcm interface on the BCM43455 can connect to linear pcm codec devices in master or slave mode. in master mode, the BCM43455 generates the pcm_clk and pcm_sync signals, and in slave mode, these signals are provided by another master on the pcm interface and are inputs to the BCM43455. the configuration of the pcm interface may be adjusted by the host through the use of vendor-specific hci commands. slot mapping the BCM43455 supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by using a time-slotting scheme where the 8 khz or 16 khz audio sample interval is divided into as many as 16 slots. the number of slots is dependent on the selected interface rate of 128 khz, 512 khz, or 1024 khz. the corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. the pcm data output driver tristates its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its output after the falling edge of the pcm clock during the last bit of the slot. frame synchronization the BCM43455 supports both short- and long-frame synchronization in both master and slave modes. in short- frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. in long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. data formatting the BCM43455 may be configured to generate and accept several different data formats. for conventional narrowband speech mode, the BCM43455 uses 13 of the 16 bits in each pcm frame. the location and order of these 13 bits can be configured to support various data formats on the pcm interface. the remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. the default format is 13-bit 2?s complement data, left justified, and clocked msb first. pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 49 wideband speech support when the host encodes wideband speech (wbs) packets in transparent mode, the encoded packets are transferred over the pcm bus for an esco voice connection. in this mode, the pcm bus is typically configured in master mode for a 4 khz sync rate with 16-bit samples, resulting in a 64 kbps bit rate. the BCM43455 also supports slave transparent mode using a proprietary rate-matching scheme. in sbc-code mode, linear 16-bit data at 16 khz (256 kbps rate) is transferred over the pcm bus. multiplexed bluetooth over pcm bluetooth supports multiple audio streams within the bluetooth channel and both 16 khz and 8 khz streams can be multiplexed. this mode of operation is only supported when the bluetooth host is the master. figure 10 shows the operation of the multiplexed transport with three simultaneous sco connections. to accommodate additional sco channels, the transport clock speed is increased. to change between modes of operation, the transport must be halted and restarted in the new configuration. figure 10: functional multiplex data diagram burst pcm mode in this mode of operation, the pcm bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. in this mode of operation, the pcm bus can operate at a rate of up to 24 mhz. this mode of operation is initiated with an hci command from the host. pcm_sync pcm_in pcm_out bt sco 1 tx bt sco 2 tx bt sco 3 tx bt sco 1 rx bt sco 2 rx bt sco 3 rx 1 frame pcm_clk 16 bits per sco frame clk each sco channel duplicates the data 6 times. each wbs frame duplicates the data 3 times per frame pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 50 pcm interface timing short frame sync, master mode figure 11: pcm timing diagram (short frame sync, master mode) table 6: pcm interface timing specifications (short frame sync, master mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high impedance 7 pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 51 short frame sync, slave mode figure 12: pcm timing diagram (short frame sync, slave mode) table 7: pcm interface timing specifications (short frame sync, slave mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high impedance 8 pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 52 long frame sync, master mode figure 13: pcm timing diagram (long frame sync, master mode) table 8: pcm interface timing specifications (long frame sync, master mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high impedance 7 bit 0 bit 0 bit 1 bit 1 pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 53 long frame sync, slave mode figure 14: pcm timing diagram (long frame sync, slave mode) table 9: pcm interface timing specifications (long frame sync, slave mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high impedance 8 bit 0 bit 0 bit 1 bit 1 pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 54 short frame sync, burst mode figure 15: pcm burst mode timing (receive only, short frame sync) table 10: pcm burst mode (receive only, short frame sync) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 pcm interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 55 long frame sync, burst mode figure 16: pcm burst mode timing (receive only, long frame sync) table 11: pcm burst mode (receive only, long frame sync) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 bit 0 bit 1 uart interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 56 uart interface the uart is a standard 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the interface features an automatic baud rate detection capability that returns a baud rate selection. alternatively, the baud rate may be selected through a vendor-specific uart hci command. uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the ahb interface through either dma or the cpu. the uart supports the bluetooth 4.1 uart hci specification: h4, a custom extended h4, and h5. the default baud rate is 115.2 kbaud. the uart supports the 3-wire h5 uart transport, as described in the bluetooth specification ( three-wire uart transport layer ). compared to h4, the h5 uart transport reduces the number of signal lines required by eliminating the cts and rts signals. the BCM43455 uart can perform xon/xoff flow control and includes hardware support for the serial line input protocol (slip). it can also perform wake-on activity. for example, activity on the rx or cts inputs can wake the chip from a sleep state. normally, the uart baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detection, and the host does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. the BCM43455 uarts operate correctly with the host uart as long as the combined baud rate error of the two devices is within 2%. table 12: example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00 i 2 s interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 57 figure 17: uart timing i 2 s interface the BCM43455 supports an i 2 s digital audio port for bluetooth audio. the i 2 s signals are: ?i 2 s clock: i 2 s sck ?i 2 s word select: i 2 s ws ?i 2 s data out: i 2 s sdo ?i 2 s data in: i 2 s sdi i 2 s sck and i 2 s ws become outputs in master mode and inputs in slave mode, while i 2 s sdo always stays as an output. the channel word length is 16 bits and the data is justified so that the msb of the left-channel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the msb of each data word is transmitted one bit clock cycle after the i 2 s ws transition, synchronous with the falling edge of bit clock. left-channel data is transmitted when i 2 s ws is low, and right-channel data is transmitted when i 2 s ws is high. data bits sent by the BCM43455 are synchronized with the falling edge of i2s_sck and should be sampled by the receiver on the rising edge of i2s_ssck. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the input reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz. table 13: uart timing specifications ref characteristics min. typ. max. unit 1 delay time, bt_uart_cts_n low to bt_uart_txd valid ? ? 1.5 bit periods 2 setup time, bt_uart_cts_n high before midpoint of stop bit ? ? 0.5 bit periods 3 delay time, midpoint of stop bit to bt_uart_rts_n high ? ? 0.5 bit periods bt_uart_cts_n bt_uart_rxd bt_uart_rts_n 1 2 midpoint of stop bit bt_uart_txd 3 midpoint of stop bit i 2 s interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 58 i 2 s timing note: timing values specified in ta b le 1 4 are relative to high and low threshold levels. table 14: timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min. max. min. max. min. max. min. max. clock period t t tr ???t r ??? a a. the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. master mode: clock generated by transmitter or receiver high t hc 0.35t tr ???0.35t tr ??? b b. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. for this reason, t hc and t lc are specified with respect to t. lowt lc 0.35t tr ???0.35t tr ??? b slave mode: clock accepted by transmitter or receiver high t hc ? 0.35t tr ???0.35t tr ?? c c. in slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal. so long as the minimum periods are greater than 0.35t r , any clock that meets the requirements can be used. low t lc ? 0.35t tr ???0.35t tr ?? c rise time t rc ??0.15t tr ????? d d. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitter driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefore, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . transmitter delay t dtr ???0.8t???? e e. to allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and t, always giving the receiver sufficient setup time. hold time t htr 0??????? d receiver setup time t sr ?????0.2t r ?? f f. the data setup and hold time must not be less than the specified receiver setup and hold time. hold time t hr ?????0?? f i 2 s interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 59 figure 18: i 2 s transmitter timing figure 19: i 2 s receiver timing note: the time periods specified in figure 18 and figure 19 are defined by the transmitter speed. the receiver specifications must match transmitter performance. sd and ws sck v l = 0.8v t lc >0.35t t rc * t hc >0.35t t v h = 2.0v t htr >0 t otr <0.8t t = clock period t tr = minimum allowed clock period for transmitter t = t tr * t rc is only relevant for transmitters in slave mode. sd and ws sck v l = 0.8v t lc > 0.35t t hc >0.35 t v h = 2.0v t hr >0 t sr >0.2t t = clock period t r = minimum allowed clock period for transmitter t > t r fm receiver subsystem BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 60 section 8: fm receiver subsystem fm radio the BCM43455 includes a completely integrated fm radio receiver with rds/rbds covering all fm bands from 65 mhz to 108 mhz. the receiver is controlled through commands on the hci. fm received audio is available in analog form or in digital form through i 2 s or pcm. the fm radio operates from the external clock reference. digital fm audio interfaces the fm audio can be transmitted via the shared pcm and i 2 s pins, and the sampling rate is programmable. the BCM43455 supports a three-wire pcm or i 2 s audio interface in either master or slave configuration. the master or slave configuration is selected using vendor specific commands over the hci interface. in addition, multiple sampling rates are supported, derived from either the fm or bluetooth clocks. in master mode, the clock rate is either of the following: ? 48 khz x 32 bits per frame = 1.536 mhz ? 48 khz x 50 bits per frame = 2.400 mhz in slave mode, any clock rate is supported up to a maximum of 3.072 mhz. fm over bluetooth the BCM43455 can output received fm audio onto bluetooth using one of following three links: esco, wbs, and a2dp. in all of the above modes, once the link has been set up, the host processor can enter sleep mode while the BCM43455 continues to stream fm audio to the remote bluetooth device, allowing the system current consumption to be minimized. esco in this use case, the stereo fm audio is downsampled to 8 khz and a mono or stereo stream is then sent through the bluetooth esco link to a remote bluetooth device, typically a headset. two bluetooth voice connections must be used to transport stereo. wideband speech link BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 61 wideband speech link in this case, the stereo fm audio is downsampled to 16 khz and a mono or stereo stream is then sent through the bluetooth wideband speech link to a remote bluetooth device, typically a headset. two bluetooth voice connections must be used to transport stereo. a2dp in this case, the stereo fm audio is encoded by the on-chip sbc encoder and transported as an a2dp link to a remote bluetooth device. sampling rates of 48 khz, 44.1 khz, and 32 khz joint stereo are supported. an a2dp ?lite? stack is implemented in the BCM43455 to support this use case, which eliminates the need to route the sbc-encoded audio back to the host to create the a2dp packets. autotune and search algorithms the BCM43455 supports a number of fm search and tune functions that allows the host to implement many convenient user functions, which are accessed through the broadcom fm stack. ? tune to play?allows the fm receiver to be programmed to a specific frequency. ? search for snr > threshold?checks the power level of the available channel and the estimated snr of the channel to help achieve precise control of the expected sound quality for the selected fm channel. specifically, the host can adjust its snr requirements to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels. ? alternate frequency jump?allows the fm receiver to automatically jump to an alternate fm channel that carries the same information, but has a better snr. for example, when traveling, a user may pass through a region where a number of channels carry the same station. when the user passes from one area to the next, the fm receiver can automatically switch to another channel with a stronger signal to spare the user from having to manually change the channel to continue listening to the same station. audio features BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 62 audio features a number of features are implemented in the BCM43455 to provide the best possible audio experience for the user. ? mono/stereo blend, switch, or fme?the BCM43455 provides automatic control of the stereo or mono settings based on the fm signal carrier-to-noise ratio (c/n). this feature is used to maintain the best possible audio snr based on the fm channel condition. three modes of operation are supported: ? blend: in this mode, fine control of stereo separation is used to achieve optimal audio quality over a wide range of input c/n. the amount of separation is fully programmable. in figure 20 , the separation is programmed to maintain a minimum 50 db snr across the blend range. ? extended blend: in this mode, stereo separation is maximized across a wide range of input cnr. broadcom static suppression typically gives a static-free user experience to within 3 db of ultimate sensitivity. ? switch: in this mode, the audio switches from full stereo to full mono at a predetermined level to maintain optimal audio quality. the stereo-to-mono switch point and the mono-to-stereo switch points are fully programmable to provide the desired amount of audio snr. in figure 21 on page 63 , the switch point is programmed to switch to mono to maintain a 40 db snr. ? fm enhancement (fme): in this mode, advanced digital signal processing in the fm receiver greatly enhances the stereo separation of the received audio. traditional fm receivers deliver a full stereo signal at a high carrier-to-noise ratio (cnr) and gradually blend into mono as the cnr drops. the broadcom stereo extension allows full stereo separation to within 2 db of the fm receiver sensitivity threshold. the same signal processing delays the onset of pops at the fm sensitivity threshold and reduces the ambient background noise by more than 20 db in the low cnr region near sensitivity. the result is a low-noise full stereo signal at input rf levels lower than previously achievable. figure 20: audio snr for blend, switch, and fme modes audio features BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 63 figure 21: stereo separation for blend, switch, and fme modes ? soft mute?improves the user experience by dynamically muting the output audio proportionate to the fm signal c/n. this prevents the user from being assaulted with a blast of static. the mute characteristic is fully programmable to accommodate fine tuning of the output signal level. an example mute characteristic is shown in figure 22 . figure 22: example soft mute characteristic rds/rbds BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 64 ? high cut?a programmable high-cut filter is provided to reduce the amount of high-frequency noise caused by static in the output audio signal. like the soft mute circuit, it is fully programmable to allow for any amount of high cut based on the fm signal c/n. ? audio pause detect?the fm receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. this feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. filtering techniques are used within the audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection. ? automatic antenna tuning?the BCM43455 has an on-chip automatic antenna tuning network. when used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength for the desired frequency. the high-q nature of this matching network simultaneously provides out-of-band blocking protection as well as a reduction of radiated spurious emissions from the fm antenna. it is designed to accommodate a wide range of external wire antennas. rds/rbds the BCM43455 integrates a rds/rbds modem and codec, the decoder includes programmable filtering and buffering functions, and the encoder includes the option to encode messages to ps or rt frame format with programmable scrolling in ps mode. the rds/rbds data can be read out in receive mode or delivered in transmit mode through either the hci interface. in addition, the rds/rbds functionality supports the following: receive ? block decoding, error correction and synchronization ? flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (it is possible to set up the BCM43455 such that synchronization is achieved when a minimum of two good blocks (error free) are decoded in sequence. the number of good blocks required for sync is programmable.) ? storage capability up to 126 blocks of rds data ? full or partial block b match detect and interrupt to host ? audio pause detection with programmable parameters ? program identification (pi) code detection and interrupt to host ? automatic frequency jump ? block e filtering ? soft mute ? signal dependent mono/stereo blend ? programmable pre-emphasis wlan global functions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 65 section 9: wlan global functions wlan cpu and memory subsystem the BCM43455 wlan section includes an integrated arm cortex-r4 32-bit processor with internal ram and rom. the arm cortex-r4 is a low-power processor that features low gate count, low interrupt latency, and low- cost debug capabilities. it is intended for deeply embedded applications that require fast interrupt response features. delivering more than 30% performance gain over arm7tdmi, the arm cortex-r4 implements the arm v7-r architecture with support for the thumb-2 instruction set. at 0.19 w/mhz, the cortex-r4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. using multiple technologies to reduce cost, the arm cortex-r4 offers improved memory utilization, reduced pin overhead, and reduced silicon area. it supports independent buses for code and data access (icode/dcode and system buses), and extensive debug features including real time trace of program execution. on-chip memory for the cpu includes 800 kb sram and 704 kb rom. one-time programmable memory various hardware configuration parameters may be stored in an internal 6144-bit (768 bytes) one-time programmable (otp) memory, which is read by the system software after device reset. in addition, customer- specific parameters, including the system vendor id and the mac address can be stored, depending on the specific board design. the initial state of all bits in an unprogrammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the broadcom wlan manufacturing test tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. gpio interface the following number of general-purpose i/o (gpio) pins are available on the wlan section of the BCM43455 that can be used to connect to various external devices: ? wlbga package ? 15 gpios upon power-up and reset, these pins become tristated. subsequently, they can be programmed to be either input or output pins via the gpio control register. in addition, the gpio pins can be assigned to various other functions. external coexistence interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 66 external coexistence interface an external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as gps or lte to manage wireless medium sharing for optimum performance. figure 23 shows the wci-2 lte coexistence interface. see table 13: ?uart timing specifications,? on page 57 for uart baud rate. figure 23: broadcom gci or bt-sig wci-2 lte coexistence interface figure 24 and table 15 on page 66 define an alternate 3-wire lte coexistence interface. figure 24: 3-wire lte coexistence interface table 15: 3-wire external coexistence interface gpio name coexistence signal type comment gpio_2 ercx_wl_prio output notify lte of request to sleep gpio_3 ercx_lte_tx input notify wlan rx of requirement to sleep gpio_4 ercx_lte_rx input notify wlan tx to reduce tx power lte\ic wlan bt uart_in uart_out seci_out / bt_txd / gpio5 ? seci_out/bt_txd and seci_in/bt_rxd on the bcm4345x are multiplexed on gpio5 and gpio4, respectively. ? the 2-wire lte coexistence interface is intended for future com patibility with the bt sig 2-wire interface that is being standa rdized for core 4.1. ? oring to generate ism_rx_priority for ercx_txconf or bt_rx_priority is achieved by setting the gpio mask registers appropriately. notes: seci_in / bt_rxd / gpio4 gci BCM43455 lte\ic wlan bt gpio2 gpio3 gpio4 ercx_wl_prio ercx_ltetx ercx_lterx ercx BCM43455 uart interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 67 uart interface a high-speed 4-wire cts/rts uart interface can be enabled by software as an alternate function on gpio pins. provided primarily for debugging during development, this uart enables the BCM43455 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is compatible with the industry standard 16550 uart, and provides a fifo size of 64 8 in each direction. jtag/swd interface the BCM43455 supports ieee 1149.1 jtag boundary scan and reduced pin-count serial wire debug (swd) mode to access the chip?s internal blocks and backplane for system bring-up and debugging. this interface allows broadcom engineers to assist customers with proprietary debug and characterization test tools. it is highly recommended that customers provide access to at least the swd pins on all pcb designs by using either test points or a header. the swd interface uses two of the jtag signals: tms for bidirectional data (swdio) and tck for the clock (swclk). the debug access port (dap) embedded in the arm processor supports both swd and jtag interfaces and can be switched from one to the other through a specific sequence on the tms/swd lines. in addition to the arm debug interface, an internal jtag master on the dap allows access to test access points (taps) in the BCM43455 for hardware debugging. wlan host interfaces BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 68 section 10: wlan host interfaces sdio v3.0 all three package options of the BCM43455 wlan section provide support for sdio version 3.0, including the new uhs-i modes: ? ds: default speed (ds) up to 25 mhz, including 1- and 4-bit modes (3.3v signaling). ? hs: high speed up to 50 mhz (3.3v signaling). ? sdr12: sdr up to 25 mhz (1.8v signaling). ? sdr25: sdr up to 50 mhz (1.8v signaling). ? sdr50: sdr up to 100 mhz (1.8v signaling). ? sdr104: sdr up to 208 mhz (1.8v signaling) ? ddr50: ddr up to 50 mhz (1.8v signaling). the sdio interface also has the ability to map the interrupt signal on to a gpio pin for applications requiring an interrupt different from the one provided by the sdio interface. the ability to force control of the gated clocks from within the device is also provided. sdio mode is enabled by strapping options. see table 20 on page 91 for strapping options. the following three functions are supported: ? function 0 standard sdio function (max blocksize/bytecount = 32b) ? function 1 backplane function to access the internal system-on-chip (soc) address space (max blocksize/bytecount = 64b) ? function 2 wlan function for efficient wlan packet transfer through dma (max blocksize/bytecount = 512b). note: the BCM43455 is backward compatible with sdio v2.0 host interfaces. sdio v3.0 BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 69 sdio pins figure 25: signal connections to sdio host (sd 4-bit mode) figure 26: signal connections to sdio host (sd 1-bit mode) table 16: sdio pin description sd 4-bit mode sd 1-bit mode data0 data line 0 data data line data1 data line 1 or interrupt irq interrupt data2 data line 2 or read wait rw read wait data3 data line 3 n/c not used clk clock clk clock cmd command line cmd command line note: per section 6 of the sdio specification, pull-ups in the 10 k ? to 100 k ? range are required on the four data lines and the cmd line. this requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the sdio host?s internal pull-ups. sd host clk cmd dat[3:0] BCM43455 sd host clk cmd data irq rw BCM43455 pci express interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 70 pci express interface the pci express (pcie) core on the BCM43455 is a high-performance serial i/o interconnect that is protocol compliant and electrically compatible with the pci express base specification v2.0 . this core contains all the necessary blocks, including logical and electrical functional subblocks to perform pcie functionality and maintain high-speed links, using existing pci system configuration software implementations without modification. organization of the pcie core is in logical layers: transaction layer, data link layer, and physical layer, as shown in figure 27 . a configuration or link management block is provided for enumerating the pcie configuration space and supporting generation and reception of system management messages by communicating with pcie layers. each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and BCM43455 device. the transmit side processes outbound packets while the receive side processes inbound packets. packets are formed and generated in the transaction and data link layer for transmission onto the high-speed links and onto the receiving device. a header is added at the beginning to indicate the packet type and any other optional fields. figure 27: pci express layer model transaction layer data link layer logical subblock electrical subblock physical layer transaction layer data link layer logical subblock electrical subblock physical layer hw/sw interface hw/sw interface tx rx tx rx pci express interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 71 transaction layer interface the pcie core employs a packet-based protocol to transfer data between the host and BCM43455 device, delivering new levels of performance and features. the upper layer of the pcie is the transaction layer. the transaction layer is primarily responsible for assembly and disassembly of transaction layer packets (tlps). tlp structure contains header, data payload, and end-to-end crc (ecrc) fields, which are used to communicate transactions, such as read and write requests and other events. a pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with credit-based flow control of tlp, which eliminates wasted link bandwidth due to retries. data link layer the data link layer serves as an intermediate stage between the transaction layer and the physical layer. its primary responsibility is to provide reliable, efficient mechanism for the exchange of tlps between two directly connected components on the link. services provided by the data link layer include data exchange, initialization, error detection and correction, and retry services. data link layer packets (dllps) are generated and consumed by the data link layer. dllps are the mechanism used to transfer link management information between data link layers of the two directly connected components on the link, including tlp acknowledgment, power management, and flow control. physical layer the physical layer of the pcie provides a handshake mechanism between the data link layer and the high-speed signaling used for link data interchange. this layer is divided into the logical and electrical functional subblocks. both subblocks have dedicated transmit and receive units that allow for point-to-point communication between the host and BCM43455 device. the transmit section prepares outgoing information passed from the data link layer for transmission, and the receiver section identifies and prepares received information before passing it to the data link layer. this process involves link initialization, configuration, scrambler, and data conversion into a specific format. logical subblock the logical sub block primary functions are to prepare outgoing data from the data link layer for transmission and identify received data before passing it to the data link layer. scrambler/descrambler this pcie phy component generates pseudo-random sequence for scrambling of data bytes and the idle sequence. on the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. on the receive side, descrambling is applied to characters after 8b/10b decoding. scrambling may be disabled in polling and recovery for testing and debugging purposes. pci express interface BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 72 8b/10b encoder/decoder the pcie core on the BCM43455 uses an 8b/10b encoder/decoder scheme to provide dc balancing, synchronizing clock and data recovery, and error detection. the transmission code is specified in the ansi x3.230-1994, clause 11 and in ieee 802.3z, 36.2.4. using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group, respectively. the control bit in conjunction with the data character is used to identify when to encode one of the twelve special symbols included in the 8b/10b transmission code. these code groups are concatenated to form a 10-bit symbol, which is then transmitted serially. special symbols are used for link management, frame tlps, and dllps, allowing these packets to be quickly identified and easily distinguished. elastic fifo an elastic fifo is implemented in the receiver side to compensate for the differences between the transmit clock domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. as a result, the transmit and receive clocks can shift one clock every 1666 clocks. in addition, the fifo adaptively adjusts the elastic level based on the relative frequency difference of the write and read clock. this technique reduces the elastic fifo size and the average receiver latency by half. electrical subblock the high-speed signals utilize the common mode logic (cml) signaling interface with on-chip termination and de-emphasis for best-in-class signal integrity. a de-emphasis technique is employed to reduce the effects of intersymbol interference (isi) due to the interconnect by optimizing voltage and timing margins for worst case channel loss. this results in a maximally open ?eye? at the detection point, thereby allowing the receiver to receive data with acceptable bit-error rate (ber). to further minimize isi, multiple bits of the same polarity that are output in succession are de-emphasized. subsequent same bits are reduced by a factor of 3.5 db in power. this amount is specified by pcie to allow for maximum interoperability while minimizing the complexity of controlling the de-emphasis values. the high- speed interface requires ac coupling on the transmit side to eliminate the dc common mode voltage from the receiver. the range of ac capacitance allowed is 75 nf to 200 nf. configuration space the pcie function in the BCM43455 implements the configuration space as defined in the pci express base specification v2.0 . wireless lan mac and phy BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 73 section 11: wireless lan mac and phy ieee 802.11ac mac the BCM43455 wlan mac is designed to support high-throughput operation with low-power consumption. it does so without compromising the bluetooth coexistence policies, thereby enabling optimal performance over both networks. in addition, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 28 . the following sections provide an overview of the important modules in the mac. figure 28: wlan mac architecture embedded cpu interface host registers, dma engines tx-fifo (32 kb) wep tkip, aes, wapi txe tx a-mpdu rxe pmq psm shared memory (6 kb) psm ucode memory ext- ihr ifs backoff, btcx tsf nav ihr bus shm bus mac-phy interface rx-fifo (10 kb) rx a-mpdu ieee 802.11ac mac BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 74 the BCM43455 wlan media access controller (mac) supports features specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the key mac features include: ? enhanced mac for supporting ieee 802.11ac features ? transmission and reception of aggregated mpdus (a-mpdu) for high throughput (ht) ? support for power management schemes, including wmm power-save, power-save multi-poll (psmp) and multiphase psmp operation ? support for immediate ack and block-ack policies ? interframe space timing support, including rifs ? support for rts/cts and cts-to-self frame sequences for protecting frame exchanges ? back-off counters in hardware for supporting multiple priorities as specified in the wmm specification ? timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware ? hardware offload for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management ? support for coexistence with bluetooth and other external radios ? programmable independent basic service set (ibss) or infrastructure basic service set functionality ? statistics counters for mib support psm the programmable state machine (psm) is a microcoded engine, which provides most of the low-level control to the hardware, to implement the ieee 802.11 specification. it is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. the instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microcode memory. it uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory (similar to a register bank) to store frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines, by programming internal hardware registers (ihr). these ihrs are co-located with the hardware functions they control, and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations the operands are obtained from shared memory, scratchpad, ihrs, or instruction literals, and the results are written into the shared memory, scratchpad, or ihrs. there are two basic branch instructions: conditional branches and alu based branches. to better support the many decision points in the ieee 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition signals are available to the psm without polling the ihrs), or on the results of alu operations. ieee 802.11ac mac BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 75 wep the wired equivalent privacy (wep) engine encapsulates all the hardware accelerators to perform the encryption and decryption, and mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, wpa2 aes-ccmp. the psm determines, based on the frame type and association information, the appropriate cipher algorithm to be used. it supplies the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames. txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with wep module to encrypt frames, and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fifos. the mac supports multiple logical queues to support traffic streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to schedule a queue from which the next frame is transmitted. once the frame is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for transmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of the mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interface and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteria such as receiver address, bssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of the containers, and disaggregate them into component mpdus. ifs the ifs module contains the timers required to determine interframe space timing including rifs timing. it also contains multiple backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). ieee 802.11ac phy BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 76 the backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. when the backoff counters reach 0, the txe gets notified, so that it may commence frame transmission. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initialized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires the mac is restored to its functional state. the psm updates the tsf timer based on the sleep duration ensuring that the tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and downlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the duration field of mac frames. this ensures that the mac complies with the protection mechanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs module, which uses it as a virtual carrier- sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from/to the phy. in addition, there is an programming interface, which can be controlled either by the host or the psm to configure and control the phy. ieee 802.11ac phy the BCM43455 wlan digital phy is designed to comply with ieee 802.11ac and ieee 802.11a/b/g/n single- stream specifications to provide wireless lan connectivity supporting data rates from 1 mbps to 433.3 mbps for low-power, high-performance handheld applications. ieee 802.11ac phy BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 77 the phy has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. it incorporates optimized implementations of the filters, fft and viterbi decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802.11g/11b hybrid networks with bluetooth coexistence. it has also been designed for shared single antenna systems between wl and bt to support simultaneous rx-rx. the key phy features include: ? programmable data rates from mcs0?mcs9 in 20, 40, and 80 mhz channels, as specified in ieee 802.11ac. ? supports optional short gi and green field modes in tx and rx. ? tx and rx ldpc for improved range and power efficiency. ? all scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive direction. ? supports ieee 802.11h/k for worldwide operation. ? advanced algorithms for low power, enhanced sensitivity, range, and reliability. ? algorithms to improve performance in presence of bluetooth. ? automatic gain control scheme for blocking and non blocking application scenario for cellular applications. ? closed loop transmit power control. ? digital rf chip calibration algorithms to handle cmos rf chip non-idealities. ? on-the-fly channel frequency and transmit power selection. ? supports per-packet rx antenna diversity. ? available per-packet channel quality and signal strength measurements. ? designed to meet fcc and other worldwide regulatory requirements. figure 29: wlan phy block diagram filters and radio comp frequency and timing synch carrier sense, agc, and rx fsm radio control block common logic block filters and radio comp afe and radio mac interface buffers ofdm demodulate viterbi decoder tx fsm pa comp modulation and coding frame and scramble fft/ifft cck/dsss demodulate descramble and deframe coex modulate/ spread wlan radio subsystem BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 78 section 12: wlan radio subsystem the BCM43455 includes an integrated dual-band wlan rf transceiver that has been optimized for use in 2.4 ghz and 5 ghz wireless lan systems. it has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism or 5 ghz u-nii bands. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. ten rf control signals are available to drive external rf switches and support optional external power amplifiers and low-noise amplifiers for each band. see the reference board schematics for further details. a block diagram of the radio subsystem is shown in figure 30 on page 79 . note that integrated on-chip baluns (not shown) convert the fully differential transmit and receive paths to single-ended signal pins. receiver path the BCM43455 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band or the entire 5 ghz u-nii band. an on-chip low-noise amplifier (lna) in the 2.4 ghz path is shared between the bluetooth and wlan receivers, while the 5 ghz receive path has a dedicated on-chip lna. control signals are available that can support the use of optional lnas for each band, which can increase the receive sensitivity by several db. transmit path baseband data is modulated and upconverted to the 2.4 ghz ism or 5-ghz u-nii bands, respectively. linear on-chip power amplifiers are included, which are capable of delivering high output powers while meeting ieee 802.11ac and ieee 802.11a/b/g/n specifications without the need for external pas. when using the internal pas, closed-loop output power control is completely integrated. as an option, external pas can be used for even higher output power, in which case the closed-loop output power control is provided by means of a-band and g-band tssi inputs from external power detectors. calibration the BCM43455 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations across components. these calibration routines are performed periodically in the course of normal radio operation. examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance, and loft calibration for carrier leakage reduction. in addition, i/q calibration, r calibration, and vco calibration are performed on-chip. no per-board calibration is required in manufacturing test, which helps to minimize the test time and cost in large volume production. calibration BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 79 figure 30: radio functional block diagram gm bt logen wl logen bt pll wl pll wlan bb bt bb clb voltage regulators bt lpo/ext lpo/rcal wl adc bt adc bt dac wl pa wl pga wl tx g-mixer wl dac wl a-pa wl a-pad wl a-pga wl tx a-mixer wl txlpf wl rxlpf wl rx a-mixer wl rx g-mixer wl a-lna11 wl a-lna12 slna wl g-lna12 bt lna load bt lna gm bt pa bt rx mixer bt tx mixer bt rxlpf bt txlpf shared xo wl txlpf wl dac wl adc wl rxlpf wl atx wl grx wl gtx wl arx bt tx bt rx bt adc bt rxlpf bt dac ball map and pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 80 section 13: ball map and pin descriptions ball map figure 31: 140-ball wlbga map?bottom view (balls facing up) 1110987654321 a pcie_tdn pcie_rdn pcie_rdp sdio_clk sdio_dat a_3 ldo_vddb at5v vout_3p3 ldo_vdd1 p5 sr_vddba t5v sr_pvss a b pcie_ref clkp pcie_tdp pcie_rxt x_avdd1p 2 pcie_clk req_l sdio_dat a_1 sdio_dat a_2 vout_btl do2p5 vout_lnl do vout_cld o vout_pci eldo sr_vlx b c pcie_ref clkn pcie_pll_ avdd1p2 pcie_vss vddc sdio_dat a_0 sdio_cmd vssc wl_reg_ on bt_reg_o n pmu_avss gpio_0 c d gpio_13 gpio_14 nc1 perst_l pci_pme_ l vddio_sd vddio gpio_2 gpio_1 gpio_3 gpio_6 d e nc2 avss_bbp ll avdd_bbp ll nc3 vddio_rf rf_swct rl_8 jtag_sel gpio_4 gpio_5 vddc gpio_7 e f rf_sw_ct rl_0 rf_sw_ct rl_1 vssc vddc rf_swct rl_4 rf_swct rl_7 vssc gpio_9 gpio_10 bt_vddc lpo_in f g wrf_xtal _xon wrf_xtal _gnd1p2 rf_sw_ct rl_2 rf_sw_ct rl_3 rf_swct rl_5 rf_swct rl_6 gpio_8 bt_vddo bt_pcm_s ync vssc bt_pcm_i n g h wrf_xtal _xop wrf_xtal _vdd1p35 wrf_xtal _vdd1p2 wrf_syn th_vdd3p 3 bt_gpio_ 3 bt_gpio_ 4 nc bt_pcm_o ut bt_i2s_do bt_pcm_c lk h j wrf_pmu _vdd1p35 wrf_syn th_vdd1p 2 wrf_syn th_gnd wrf_vco _gnd bt_gpio_ 2 bt_uart_ cts_n vddc bt_vddc bt_i2s_w s bt_i2s_di bt_i2s_cl k j k wrf_rx5 g_gnd wrf_afe_ vdd1p35 wrf_gen eral_gnd wrf_ext_ tssia gpio_15 gpio_16 vssc bt_gpio_ 5 bt_uart_ rts_n bt_uart_ txd bt_uart_ rxd k l wrf_rfin _5g wrf_gen eral2_gn d wrf_afe_ gnd wrf_gpai o_out bt_lnavd d1p2 bt_ifvss bt_pllvs s bt_clk_r eq bt_host_ wake vssc bt_vddc l m wrf_pao ut_5g wrf_pa_ gnd3p3 wrf_txmi x_vdd wrf_rx2 g_gnd bt_lnavs s bt_pavss bt_pllvd d1p2 fm_pllvs s fm_rfvss fm_pllvd d1p2 bt_dev_w ake m n wrf_pa_v dd3p3 wrf_pao ut_2g wrf_rfin _2g bt_rf bt_pavdd 2p5 bt_ifvdd1 p2 fm_rfin fm_rfvdd 1p2 fm_aout2 fm_aout1 n 1110987654321 pin list by pin number BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 81 pin list by pin number ta b l e 1 7 lists BCM43455 pins by pin number. for a list of BCM43455 pins by pin name, see table 18 on page 83 . table 17: wlbga pin list by pin number ball name a1 sr_pvss a2 sr_vddbat5v a3 ldo_vdd1p5 a4 vout_3p3 a5 ldo_vddbat5v a6 sdio_data_3 a7 sdio_clk a8 pcie_rdp a9 pcie_rdn a10 pcie_tdn a11 ? b1 sr_vlx b2 vout_pcieldo b3 vout_cldo b4 vout_lnldo b5 vout_btldo2p5 b6 sdio_data_2 b7 sdio_data_1 b8 pcie_clkreq_l b9 pcie_rxtx_avdd1p2 b10 pcie_tdp b11 pcie_refclkp c1 gpio_0 c2 pmu_avss c3 bt_reg_on c4 wl_reg_on c5 vssc c6 sdio_cmd c7 sdio_data_0 c8 vddc c9 pcie_vss c10 pcie_pll_avdd1p2 c11 pcie_refclkn d1 gpio_6 d2 gpio_3 d3 gpio_1 d4 gpio_2 d5 vddio d6 vddio_sd d7 pci_pme_l d8 perst_l d9 nc1 d10 gpio_14 d11 gpio_13 e1 gpio_7 e2 vddc e3 gpio_5 e4 gpio_4 e5 jtag_sel e6 rf_sw_ctrl_8 e7 vddio_rf e8 nc3 e9 avdd_bbpll e10 avss_bbpll e11 nc2 f1 lpo_in f2 bt_vddc f3 gpio_10 f4 gpio_9 f5 vssc f6 rf_sw_ctrl_7 f7 rf_sw_ctrl_4 f8 vddc f9 vssc f10 rf_sw_ctrl_1 f11 rf_sw_ctrl_0 table 17: wlbga pin list by pin number (cont.) ball name pin list by pin number BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 82 g1 bt_pcm_in g2 vssc g3 bt_pcm_sync g4 bt_vddo g5 gpio_8 g6 rf_sw_ctrl_6 g7 rf_sw_ctrl_5 g8 rf_sw_ctrl_3 g9 rf_sw_ctrl_2 g10 wrf_xtal_gnd1p2 g11 wrf_xtal_xon h1 bt_pcm_clk h2 bt_i2s_do h3 bt_pcm_out h4 nc h5 bt_gpio_4 h6 bt_gpio_3 h7 ? h8 wrf_synth_vdd3p3 h9 wrf_xtal_vdd1p2 h10 wrf_xtal_vdd1p35 h11 wrf_xtal_xop j1 bt_i2s_clk j2 bt_i2s_di j3 bt_i2s_ws j4 bt_vddc j5 vddc j6 bt_uart_cts_n j7 bt_gpio_2 j8 wrf_vco_gnd j9 wrf_synth_gnd j10 wrf_synth_vdd1p2 j11 wrf_pmu_vdd1p35 k1 bt_uart_rxd k2 bt_uart_txd k3 bt_uart_rts_n k4 bt_gpio_5 k5 vssc k6 gpio_16 table 17: wlbga pin list by pin number (cont.) ball name k7 gpio_15 k8 wrf_ext_tssia k9 wrf_general_gnd k10 wrf_afe_vdd1p35 k11 wrf_rx5g_gnd l1 bt_vddc l2 vssc l3 bt_host_wake l4 bt_clk_req l5 bt_pllvss l6 bt_ifvss l7 bt_lnavdd1p2 l8 wrf_gpaio_out l9 wrf_afe_gnd l10 wrf_general2_gnd l11 wrf_rfin_5g m1 bt_dev_wake m2 fm_pllvdd1p2 m3 fm_rfvss m4 fm_pllvss m5 bt_pllvdd1p2 m6 bt_pavss m7 bt_lnavss m8 wrf_rx2g_gnd m9 wrf_txmix_vdd m10 wrf_pa_gnd3p3 m11 wrf_paout_5g n1 fm_aout1 n2 fm_aout2 n3 fm_rfvdd1p2 n4 fm_rfin n5 bt_ifvdd1p2 n6 bt_pavdd2p5 n7 bt_rf n8 wrf_rfin_2g n9 wrf_paout_2g n10 ? n11 wrf_pa_vdd3p3 table 17: wlbga pin list by pin number (cont.) ball name pin list by pin name BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 83 pin list by pin name ta b l e 1 8 lists BCM43455 pins by pin name. for a list of BCM43455 pins by pin number, see table 17 on page 81 . table 18: wlbga pin list by pin name name ball avdd_bbpll e9 avss_bbpll e10 bt_clk_req l4 bt_dev_wake m1 bt_gpio_2 j7 bt_gpio_3 h6 bt_gpio_4 h5 bt_gpio_5 k4 bt_host_wake l3 bt_i2s_clk j1 bt_i2s_di j2 bt_i2s_do h2 bt_i2s_ws j3 bt_ifvdd1p2 n5 bt_ifvss l6 bt_lnavdd1p2 l7 bt_lnavss m7 bt_pavdd2p5 n6 bt_pavss m6 bt_pcm_clk h1 bt_pcm_in g1 bt_pcm_out h3 bt_pcm_sync g3 bt_pllvdd1p2 m5 bt_pllvss l5 bt_reg_on c3 bt_rf n7 bt_uart_cts_n j6 bt_uart_rts_n k3 bt_uart_rxd k1 bt_uart_txd k2 bt_vddc f2 bt_vddc j4 bt_vddc l1 bt_vddo g4 fm_aout1 n1 fm_aout2 n2 fm_pllvdd1p2 m2 fm_pllvss m4 fm_rfin n4 fm_rfvdd1p2 n3 fm_rfvss m3 gpio_0 c1 gpio_1 d3 gpio_2 d4 gpio_3 d2 gpio_4 e4 gpio_5 e3 gpio_6 d1 gpio_7 e1 gpio_8 g5 gpio_9 f4 gpio_10 f3 gpio_13 d11 gpio_14 d10 gpio_15 k7 gpio_16 k6 jtag_sel e5 ldo_vdd1p5 a3 ldo_vddbat5v a5 lpo_in f1 nc h4 nc1 d9 nc2 e11 nc3 e8 pcie_clkreq_l b8 table 18: wlbga pin list by pin name (cont.) name ball pin list by pin name BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 84 pcie_pll_avdd1p2 c10 pcie_rdn a9 pcie_rdp a8 pcie_refclkn c11 pcie_refclkp b11 pcie_rxtx_avdd1p2 b9 pcie_tdn a10 pcie_tdp b10 pcie_vss c9 pci_pme_l d7 perst_l d8 pmu_avss c2 rf_sw_ctrl_0 f11 rf_sw_ctrl_1 f10 rf_sw_ctrl_2 g9 rf_sw_ctrl_3 g8 rf_sw_ctrl_4 f7 rf_sw_ctrl_5 g7 rf_sw_ctrl_6 g6 rf_sw_ctrl_7 f6 rf_sw_ctrl_8 e6 sdio_clk a7 sdio_cmd c6 sdio_data_0 c7 sdio_data_1 b7 sdio_data_2 b6 sdio_data_3 a6 sr_pvss a1 sr_vddbat5v a2 sr_vlx b1 vddc c8 vddc e2 vddc f8 vddc j5 vddio d5 vddio_rf e7 vddio_sd d6 vout_3p3 a4 vout_btldo2p5 b5 table 18: wlbga pin list by pin name (cont.) name ball vout_cldo b3 vout_lnldo b4 vout_pcieldo b2 vssc c5 vssc f5 vssc f9 vssc g2 vssc k5 vssc l2 wl_reg_on c4 wrf_afe_gnd l9 wrf_afe_vdd1p35 k10 wrf_ext_tssia k8 wrf_general2_gnd l10 wrf_general_gnd k9 wrf_gpaio_out l8 wrf_paout_2g n9 wrf_paout_5g m11 wrf_pa_gnd3p3 m10 wrf_pa_vdd3p3 n11 wrf_pmu_vdd1p35 j11 wrf_rfin_2g n8 wrf_rfin_5g l11 wrf_rx2g_gnd m8 wrf_rx5g_gnd k11 wrf_synth_gnd j9 wrf_synth_vdd1p2 j10 wrf_synth_vdd3p3 h8 wrf_txmix_vdd m9 wrf_vco_gnd j8 wrf_xtal_gnd1p2 g10 wrf_xtal_vdd1p2 h9 wrf_xtal_vdd1p35 h10 wrf_xtal_xon g11 wrf_xtal_xop h11 ?a11 ?h7 ?n10 table 18: wlbga pin list by pin name (cont.) name ball pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 85 pin descriptions the signal name, type, and description of each pin in the BCM43455 is listed in table 19 . the symbols shown under type indicate pin directions (i/o = bidirectional, i = input, o = output) and the internal pull-up/pull-down characteristics (pu = weak internal pull-up resistor and pd = weak internal pull-down resistor), if any. table 19: signal descriptions signal name wlbga ball type description wlan and bluetooth receive rf signal interface wrf_rfin_2g n8 i 2.4 ghz bluetooth and wlan receiver shared input. wrf_rfin_5g l11 i 5 ghz wlan receiver input. wrf_paout_2g n9 o 2.4 ghz wlan pa output. wrf_paout_5g m11 o 5 ghz wlan pa output. wrf_ext_tssia k8 i 5 ghz tssi input from an optional external power amplifier/power detector. wrf_gpaio_out l8 i/o gpio or 2.4 ghz tssi input from an optional external power amplifier/power detector. rf switch control lines rf_sw_ctrl_0 f11 o programmable rf switch control lines. the control lines are programmable via the driver and nvram file. rf_sw_ctrl_1 f10 o rf_sw_ctrl_2 g9 o rf_sw_ctrl_3 g8 o rf_sw_ctrl_4 f7 o rf_sw_ctrl_5 g7 o rf_sw_ctrl_6 g6 o rf_sw_ctrl_7 f6 o rf_sw_ctrl_8 e6 o wlan pci express interface pcie_clkreq_l b8 od pcie clock request signal which indicates when the refclk to the pcie interface can be gated. 1 = the clock can be gated. 0 = the clock is required. perst_l d8 i (pu) pcie system reset. this input is the pcie reset as defined in the pcie base specification version 1.1 . pcie_rdn a9 i receiver differential pair (1 lane). pcie_rdp a8 i pcie_refclkn c11 i pcie differential clock inputs (negative and positive), 100 mhz differential. pcie_refclkp b11 i pcie_tdn a10 o transmitter differential pair (1 lane). pcie_tdp b10 o pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 86 pci_pme_l d7 od pci power management event output. used to request a change in the device or system power state. the assertion and deassertion of this signal is asynchronous to the pcie reference clock. this signal has an open-drain output structure, as per the pci bus local bus specification, revision 2.3 . wlan sdio bus interface note: these signals can also have alternate functionality depending on package and host interface mode. sdio_clk a7 i sdio clock input. sdio_cmd c6 i/o sdio command line. sdio_data_0 c7 i/o sdio data line 0. sdio_data_1 b7 i/o sdio data line 1. sdio_data_2 b6 i/o sdio data line 2. sdio_data_3 a6 i/o sdio data line 3. wlan gpio interface note: the gpio signals can be multiplexed via software and the jtag_sel pin to behave as various specific functions. gpio_0 c1 i/o programmable gpio pins: gpio_2 is tck/swclk if jtag_sel = 1 gpio_3 is tms/swdio if jtag_sel = 1 gpio_4 is tdio if jtag_sel = 1 gpio_5 is tdo if jtag_sel = 1 gpio_6 is trst_l if jtag_sel = 1 gpio_1 d3 i/o gpio_2 d4 i/o gpio_3 d2 i/o gpio_4 e4 i/o gpio_5 e3 i/o gpio_6 d1 i/o gpio_7 e1 i/o gpio_8 g5 i/o gpio_9 f4 i/o gpio_10 f3 i/o gpio_13 d11 i/o gpio_14 d10 i/o gpio_15 k7 i/o gpio_16 k6 i/o table 19: signal descriptions (cont.) signal name wlbga ball type description pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 87 jtag/swd interface jtag_sel e5 i/o jtag select. this pin must be connected to ground if the jtag/swd interface is not used. it must be high to select swd or jtag. when jtag_sel = 1: ? gpio_2 is tck/swclk ? gpio_3 is tms/swdio ? gpio_4 is tdio ? gpio_5 is tdo ? gpio_6 is trst_l clocks wrf_xtal_xop h11 i xtal oscillator input. wrf_xtal_xon g11 o xtal oscillator output. lpo_in f1 i external sleep clock input (32.768 khz). bt_clk_req l4 o reference clock request (shared by bt and wlan). bluetooth/fm transceiver bt_rf n7 o bluetooth pa output. fm_rfin n4 i fm radio antenna port. fm_aout1 n1 o fm dac output 1. fm_aout2 n2 o fm dac output 2. bluetooth pcm bt_pcm_clk h1 i/o pcm or slimbus clock; can be master (output) or slave (input). bt_pcm_in g1 i pcm data input or slimbus transport sensing. bt_pcm_out h3 o pcm data output. bt_pcm_sync g3 i/o pcm sync; can be master (output) or slave (input), or slimbus data. bluetooth uart bt_uart_cts_n j6 i uart clear-to-send. active-low clear-to- send signal for the hci uart interface. bt_uart_rts_n k3 o uart request-to-send. active-low request-to-send signal for the hci uart interface. bt led control pin. bt_uart_rxd k1 i uart serial input. serial data input for the hci uart interface. bt rf disable pin 2. bt_uart_txd k2 o uart serial output. serial data output for the hci uart interface. table 19: signal descriptions (cont.) signal name wlbga ball type description pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 88 bluetooth/fm i2s bt_i2s_clk j1 i/o i 2 s clock, can be master (output) or slave (input). bt_i2s_di j2 i/o i 2 s data input. bt_i2s_do h2 i/o i 2 s data output. bt_i2s_ws j3 i/o i 2 s ws; can be master (output) or slave (input). bluetooth gpio bt_gpio_2 j7 i/o bluetooth general-purpose i/o. bt_gpio_3 h6 i/o bluetooth general-purpose i/o. bt_gpio_4 h5 i/o bluetooth general-purpose i/o. bt_gpio_5 k4 i/o bluetooth general-purpose i/o. miscellaneous wl_reg_on c4 i used by pmu to power-up or power down the internal BCM43455 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on c3 i used by pmu to power-up or power down the internal BCM43455 regulators used by the bluetooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_dev_wake m1 i/o bluetooth dev_wake. bt_host_wake l3 i/o bluetooth host_wake. integrated voltage regulators sr_vddbat5v a2 i vbat. sr_vlx b1 o cbuck switching regulator output. refer to table 44 on page 130 for details of the inductor and capacitor required on this output. ldo_vdd1p5 a3 i lnldo input. ldo_vddbat5v a5 i ldo vbat. wrf_xtal_vdd1p35 h10 i xtal ldo input (1.35v). wrf_xtal_vdd1p2 h9 o xtal ldo output (1.2v). vout_lnldo b4 o output of lnldo. vout_cldo b3 o output of core ldo. vout_btldo2p5 b5 o output of bt ldo. table 19: signal descriptions (cont.) signal name wlbga ball type description pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 89 vout_3p3 a4 o ldo 3.3v output. bluetooth supplies bt_pavdd2p5 n6 pwr bluetooth pa power supply. bt_lnavdd1p2 l7 pwr bluetooth lna power supply. bt_ifvdd1p2 n5 pwr bluetooth if block power supply. bt_pllvdd1p2 m5 pwr bluetooth rf pll power supply. fm transceiver supplies fm_rfvdd1p2 n3 pwr fm rf power supply. fm_pllvdd1p2 m2 pwr fm pll power supply. wlan supplies wrf_synth_vdd3p3 h8 pwr synthesizer vdd 3.3v supply. wrf_pa_vdd3p3 n11 pwr 2 ghz and 5 ghz pa 3.3v vbat supply. wrf_pmu_vdd1p35 j11 pwr pmu 1.35v supply. wrf_txmix_vdd m9 pwr 3.3v supply for the tx mix. wrf_synth_vdd1p2 j10 pwr 1.2v supply for the synthesizer. wrf_afe_vdd1p35 k10 pwr 1.35v supply for the afe. miscellaneous supplies vddc c8, e2, f8, j5 pwr 1.2v core supply for the wlan. vddio d5 pwr 1.8v?3.3v vddio supply for the wlan. must be directly connected to pmu_vddo and bt_vddo on the pcb. bt_vddc f2, j4, l1 pwr 1.2v core supply for the bt. bt_vddo g4 pwr 1.8v?3.3v vddio supply for the bt. must be directly connected to pmu_vddo and vddio on the pcb. vddio_sd d6 pwr 1.8v?3.3v supply for the sdio pads. vddio_rf e7 pwr io supply for the rf switch control pads (3.3v). avdd_bbpll e9 pwr 1.2v supply for the baseband pll. pcie_pll_avdd1p2 c10 pwr 1.2v supply for the pcie pll. vout_pcieldo b2 pwr 1.2v supply for the pcie. pcie_rxtx_avdd1p2 b9 pwr 1.2v supply for the pcie tx/rx. ground wrf_vco_gnd j8 gnd vco/logen ground. wrf_afe_gnd l9 gnd afe ground. wrf_xtal_gnd1p2 g10 gnd xtal ground. wrf_rx2g_gnd m8 gnd rx 2 ghz ground. wrf_rx5g_gnd k11 gnd rx 5 ghz ground. wrf_pa_gnd3p3 m10 gnd pa ground. wrf_general_gnd k9 gnd general ground. table 19: signal descriptions (cont.) signal name wlbga ball type description pin descriptions BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 90 wrf_general2_gnd l10 gnd general ground. wrf_synth_gnd j9 gnd ground. vssc c5, f5, f9, g2, k5, l2 gnd core ground for wlan and bt. sr_pvss a1 gnd power ground. pmu_avss c2 gnd quiet ground. bt_pavss m6 gnd bluetooth pa ground. bt_lnavss m7 gnd bluetooth lna ground. bt_ifvss l6 gnd bluetooth if block ground. bt_pllvss l5 gnd bluetooth pll ground. fm_pllvss m4 gnd fm pll ground. fm_rfvss m3 gnd fm rf ground. avss_bbpll e10 gnd baseband pll ground. pcie_vss c9 gnd pcie ground. no connect nc1 d9 ? no connect. nc2 e11 nc3 e8 nc h4 ? no connect. depopulated pins ? a11, h7, n10 ? ? table 19: signal descriptions (cont.) signal name wlbga ball type description wlan gpio signals and strapping options BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 91 wlan gpio signals an d strapping options this section describes wlan gpio signals and strapping options. the pins are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each strapping option pin has an internal pull-up (pu) or pull-down (pd) resistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to gnd, using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 20: strapping options pin name strap wlbga ball default internal pull during strap description gpio_7 sdio_padvddio e1 1 default pull = 1. sdio interface voltage. 1 = 1.8v, 0 = 3.3v. default is 1.8v. gpio_16 host_iface_sdio k6 0 default is pcie. pull high during por to select sdio. broadcom ? november 5, 2015 ? 43455-ds109-r page 92 wlan gpio signals and strapping options broadcom confidential BCM43455 preliminary data sheet multiplexed bluetooth gpio signals the bluetooth gpio pins (bt_gpio_0 to bt_gpio_7) are multiplexed pins and can be programmed to be used as gpios or for other bl uetooth interface signals such as i 2 s. the specific function for a given bt_gpio_x pin is chosen by programming the pad function control register for that specific pin. ta b l e 2 1 shows the possible options for each bt_gpio_x pin. note that each bt_gpio_x pin's pad function control register setting is ind ependent (bt_gpio_5 can be set to pad function 7 at the same time that bt_gpio_3 is set to pad function 0). when the pad function control register is set to 0, the bt_gpios do not have specific functions assigned to them and behave as generic gpios. the a_gpio_x pins described below are multiplexed behind the BCM43455's pcm and i 2 s interface pins. table 21: gpio multiplexing matrix pin name pad function control register setting 0 1 2 3 4 5 6 7 15 bt_uart_cts_n uart_cts_n ? ? ? ? ? ? a_gpio[1] ? bt_uart_rts_n uart_rts_n ? ? ? ? ? ? a_gpio[0] ? bt_uart_rxd uart_rxd ? ? ? ? ? ? gpio[5] ? bt_uart_txd uart_txd ? ? ? ? ? ? gpio[4] ? bt_pcm_in a_gpio[3] pcm_in pcm_in hclk ? ? ? i2s_ssdi/msdi sf_miso bt_pcm_out a_gpio[2] pcm_out pcm_out link_ind ? i2s_msdo ? i2s_ssdo sf_mosi bt_pcm_sync a_gpio[1] pcm_sync pcm_sync hclk ? i2s_mws ? i2s_sws sf_spi_csn bt_pcm_clk a_gpio[0] pcm_clk pcm_clk ? ? i2s_msck ? i2s_ssck sf_spi_clk bt_i2s_do a_gpio[5] pcm_out ? ? i2s_ssdo i2s_msdo ? status ? bt_i2s_di a_gpio[6] pcm_in ? hclk i2s_ssdi/msdi ? ? tx_con_fx ? bt_i2s_ws gpio[7] pcm_sync ? link_ind ? i2s_mws ? i2s_sws ? bt_i2s_clk gpio[6] pcm_clk ? ? int_lpo i2s_msck ? i2s_ssck ? bt_gpio_5 gpio[5] hclk ? i2s_msck i2s_ssck ? ? clk_req ? bt_gpio_4 gpio[4] link_ind ? i2s_msdo i2s_ssdo ? ? ? ? bt_gpio_3 gpio[3] ? ? i2s_mws i2s_sws ? ? ? ? bt_gpio_2 gpio[2] ? ? ? i2s_ssdi/msdi ? ? ? ? bt_clk_req wl/bt_clk_req ? ? ? ? ? ? a_gpio[7] ? wlan gpio signals and strapping options BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 93 the multiplexed gpio signals are described in ta b le 2 2 . table 22: multiplexed gpio signals pin name type description uart_cts_n i host uart clear to send. uart_rts_n o device uart request to send. uart_rxd i device uart receive data. uart_txd o host uart transmit data. pcm_in i pcm data input. pcm_out o pcm data output. pcm_sync i/o pcm sync signal, can be master (output) or slave (input). pcm_clk i/o pcm clock, can be master (output) or slave (input). gpio[7:0] i/o general-purpose i/o. a_gpio[7:0] i/o a group general-purpose i/o. i2s_msdo o i 2 s master data output. i2s_mws o i 2 s master word select. i2s_msck o i 2 s master clock. i2s_ssck i i 2 s slave clock. i2s_ssdo o i 2 s slave data output. i2s_sws i i 2 s slave word select. i2s_ssdi/msdi i i 2 s slave/master data input. status o signals bluetooth priority status. tx_con_fx i wlan-bt coexist. transmission confirmation; permission for bt to transmit. rf_active o wlan-bt coexist. asserted (logic high) during local bt rx and tx slots. link_ind o bt receiver/transmitter link indicator. clk_req o wlan/bt clock request output. sf_spi_clk o sflash sclk: serial clock (output from master). sf_miso i sflash miso; somi: master input, slave output (output from slave). sf_mosi o sflash mosi; simo: master output, slave input (output from master). sf_spi_csn o sflash ss: slave select (active low, output from master). broadcom ? november 5, 2015 ? 43455-ds109-r page 94 i/o states broadcom confidential BCM43455 preliminary data sheet i/o states the following notations are used in table 23 : ? i: input signal ? o: output signal ? i/o: input/output signal ?pu = pulled up ? pd = pulled down ? nopull = neither pulled up nor pulled down table 23: i/o states name i/o keeper a active mode low power state/sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on = 0) and vddios are present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? bt_reg_on i n input; pd (pull down can be disabled) input; pd (pull down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? bt_clk_req i/o y open drain or push-pull (programmable). active high. open drain or push-pull (programmable). active high high-z, nopull open drain. active high open drain. active high. bt_vddo bt_host_wake i/o y input/output; pu, pd, nopull (programmable) input/output; pu, pd, nopull (programmable) high-z, nopull input, pu input, pd bt_vddo bt_dev_wake i/o y input/output; pu, pd, nopull (programmable) input; pu, pd, nopull (programmable) high-z, nopull input, pd input, pd bt_vddo bt_gpio_2, bt_gpio_3 i/o y input/output; pu, pd, nopull (programmable) input/output; pu, pd, nopull (programmable) high-z, nopull input, pd input, pd bt_vddo bt_gpio_4, bt_gpio_5 i/o y input/output; pu, pd, nopull (programmable) input/output; pu, pd, nopull (programmable) high-z, nopull input, pu input, pu bt_vddo bt_uart_cts_n i y input; nopull input; nopull high-z, nopull input; pu input; pu bt_vddo bt_uart_rts_n o y output; nopull output; nopull high-z, nopull input; pu input; pu bt_vddo bt_uart_rxd i y input; pu input; nopull high-z, nopull input; pu input; pu bt_vddo bt_uart_txd o y output; nopull output; nopull high-z, nopull input; pu input; pu bt_vddo sdio_data[0:3] i/o n input/output; pu (sdio mode) input; pu (sdio mode) high-z, nopull input; pu (sdio mode) input; pu (sdio mode) wl_vddio broadcom ? november 5, 2015 ? 43455-ds109-r page 95 i/o states broadcom confidential BCM43455 preliminary data sheet sdio_cmd i/o n input/output; pu (sdio mode) input; pu (sdio mode) high-z, nopull input; pu (sdio mode) input; pu (sdio mode) wl_vddio sdio_clk i n input; nopull input; nopull high-z, nopull input; nopull input; nopull wl_vddio bt_pcm_clk i/o y input; nopull c input; nopull c high-z, nopull input, pd input, pd bt_vddo bt_pcm_in i/o y input; nopull c input; nopull c high-z, nopull input, pd input, pd bt_vddo bt_pcm_out i/o y input; nopull c input; nopull c high-z, nopull input, pd input, pd bt_vddo bt_pcm_sync i/o y input; nopull c input; nopull c high-z, nopull input, pd input, pd bt_vddo bt_i2s_ws i/o y input; nopull d input; nopull d high-z, nopull input, pd input, pd bt_vddo bt_i2s_clk i/o y input; nopull d input; nopull d high-z, nopull input, pd input, pd bt_vddo bt_i2s_di i/o y input; nopull d input; nopull d high-z, nopull input, pd input, pd bt_vddo bt_i2s_do i/o y input; nopull d input; nopull d high-z, nopull input, pd input, pd bt_vddo gpio_0 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd wl_vddio gpio_1 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_2 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_3 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd wl_vddio gpio_4 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_5 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd wl_vddio gpio_6 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_7 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio table 23: i/o states (cont.) name i/o keeper a active mode low power state/sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on = 0) and vddios are present power rail broadcom ? november 5, 2015 ? 43455-ds109-r page 96 i/o states broadcom confidential BCM43455 preliminary data sheet gpio_8 i/o y input/output; pu, pd, nopull (programmable [default: pd]) e input/output; pu, pd, nopull (programmable [default: pd]) e high-z, nopull input; pd e input; pd e wl_vddio gpio_9 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd wl_vddio gpio_10 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_13 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_14 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_15 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_16 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio rf_sw_ctrl [0:8] i/o y output; nopull output; nopull high-z output; nopull output; nopull vddio_rf a. keeper column: n = pad has no keeper. y = pad has a keeper. keeper is always active except in power-down state. if there is n o keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to floating pad (sdio_clk, for example). b. in the power-down state (xx_reg_on=0): high-z; nopull => the pad is disabled because power is not supplied. c. depending on whether the pcm interface is enabled and the configuration of pcm is in master or slave mode, it can be either o utput or input. d. depending on whether the i 2 s interface is enabled and the configuration of i 2 s is in master or slave mode, it can be either output or input. e. nopull when in sdio mode. table 23: i/o states (cont.) name i/o keeper a active mode low power state/sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on = 0) and vddios are present power rail dc characteristics BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 97 section 14: dc characteristics absolute maximum ratings note: values in this data sheet are design goals and are subject to change based on the results of device characterization. caution! the absolute maximum ratings in table 24 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 24: absolute maximum ratings rating symbol value unit dc supply for the vbat and pa driver supply vbat ?0.5 to +6.0 v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v wrf_tcxo_vdd ? ?0.5 to 3.63 v maximum undershoot voltage for i/o a a. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o a v overshoot vddio + 0.5 v maximum junction temperature t j 125 c environmental ratings BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 98 environmental ratings the environmental ratings are shown in table 25 . electrostatic disch arge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. always store unused material in its antistatic packaging. table 25: environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85 c functional operation a a. functionality is guaranteed across this ambient temperature range. optimal rf performance specified in the data sheet, however, is guaranteed only for ?20c to 75c. storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation table 26: esd specifications pin type symbol condition minimum esd rating unit esd handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 1kv cdm esd_hand_cdm charged device model contact discharge per jedec eia/jesd22- c101 250 v recommended operating conditions and dc characteristics BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 99 recommended operating conditi ons and dc characteristics caution! functional operation is not guaranteed outside of the limits shown in table 27 . operation outside these limits for extended periods can adversely affect long-term reliability of the device. note: for dc absolute maximum rating (amr), see table 24 on page 97 . table 27: recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage for vbat vbat 3.0 a a. the BCM43455 is functional across this range of voltages. optimal rf performance specified in the data sheet, however, is guaranteed only for 3.2v < vbat < 4.8v. ? 5.25 b b. the maximum continuous voltage is 5.25v. v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for tcxo input buffer wrf_tcxo_vdd 1.62 1.8 1.98 v dc supply voltage for digital i/o vddio 1.62 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v external tssi input tssi 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ?v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ?v output low voltage @ 2 ma vol ? ?0.45 v for vddio = 3.3v: input high voltage vih 2.00 ? ?v input low voltage vil ? ?0.80 v output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40 v rf switch control output pins c c. programmable 2 ma to 16 ma drive strength. default is 10 ma. for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40 v output capacitance c out ? ? 5 pf bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 100 section 15: bluetoot h rf specifications unless otherwise stated, limit values apply for the conditions specified in table 25: ?environmental ratings,? on page 98 and table 27: ?recommended operating conditions and dc characteristics,? on page 99 . typical values apply for the following conditions: ? vbat = 3.6v ? ambient temperature +25c figure 32: port locations for bluetooth testing note: values in this data sheet are design goals and are subject to change based on device characterization results. note: all bluetooth specifications are measured at the chip port, unless otherwise defined. note: the specifications in table 28 on page 101 are measured at the chip port input, unless otherwise defined. optional filter bt pa 2g pa lna 5g lna 2g 5g pa diplexer chip port antenna port antenna port 2.4g configured with itr rf port optional filter bt pa 2g pa lna 5g lna 2g 5g pa diplexer rf port chip port 2.4g configured with etr chip port chip port chip port chip port chip port chip port rf port bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 101 table 28: bluetooth receiver rf specifications parameter conditions minimum typical maximum unit general frequency range ? 2402 ? 2480 mhz rx sensitivity a gfsk, 0.1% ber, 1 mbps ? ?93.5 ? dbm ? /4-dqpsk, 0.01% ber, 2 mbps ? ?95.5 ? dbm 8-dpsk, 0.01% ber, 3 mbps ? ?89.5 ? dbm input ip3 ? ?16 ? ? dbm maximum input at rf port ? ? ? ?20 dbm rx lo leakage 2.4 ghz band ? ? ? ?90 dbm interference performance b c/i co-channel gfsk, 0.1% ber ? ? 11 db c/i 1 mhz adjacent channelgfsk, 0.1% ber??0db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ? ?30 db c/i ? 3 mhz adjacent channel gfsk, 0.1% ber ? ? ?40 db c/i image channel gfsk, 0.1% ber ? ? ?9 db c/i 1-mhz adjacent to image channel gfsk, 0.1% ber ? ? ?20 db c/i co-channel ? /4-dqpsk, 0.1% ber ? ? 13 db c/i 1 mhz adjacent channel ? /4-dqpsk, 0.1% ber??0db c/i 2 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? ?30 db c/i ? 3 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ? ?40 db c/i image channel ? /4-dqpsk, 0.1% ber ? ? ?7 db c/i 1 mhz adjacent to image channel ? /4-dqpsk, 0.1% ber ? ? ?20 db c/i co-channel 8-dpsk, 0.1% ber ? ? 21 db c/i 1 mhz adjacent channel8-dpsk, 0.1% ber??5db c/i 2 mhz adjacent channel 8-dpsk, 0.1% ber ? ? ?25 db c/i ? 3 mhz adjacent channel 8-dpsk, 0.1% ber ? ? ?33 db c/i image channel 8-dpsk, 0.1% ber??0db c/i 1 mhz adjacent to image channel 8-dpsk, 0.1% ber ? ? ?13 db bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 102 out-of-band blocking performance (cw) 30?2000 mhz 0.1% ber ? ?10 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10 ? dbm out-of-band blocking performance, modulated interferer gfsk (1 mbps) c 698?716 mhz wcdma ? ?14 ? dbm 776?849 mhz wcdma ? ?14 ? dbm 824?849 mhz gsm850 ? ?14 ? dbm 824?849 mhz wcdma ? ?14 ? dbm 880?915 mhz e-gsm ? ?13 ? dbm 880?915 mhz wcdma ? ?13 ? dbm 1710?1785 mhz gsm1800 ? ?18 ? dbm 1710?1785 mhz wcdma ? ?17 ? dbm 1850?1910 mhz gsm1900 ? ?20 ? dbm 1850?1910 mhz wcdma ? ?19 ? dbm 1880?1920 mhz td-scdma ? ?20 ? dbm 1920?1980 mhz wcdma ? ?20 ? dbm 2010?2025 mhz td?scdma ? ?20 ? dbm 2500?2570 mhz wcdma ? ?23 ? dbm 2500?2570 mhz d band 7 ? ?25 ? dbm 2300?2400 mhz e band 40 ? ?35.2 ? dbm 2570?2620 mhz f band 38 ? ?21 ? dbm 2545?2575 mhz g xgp band ? ?22 ? dbm ? /4-dpsk (2 mbps) c 698?716 mhz wcdma ? ?10 ? dbm 776?794 mhz wcdma ? ?10 ? dbm 824?849 mhz gsm850 ? ?11 ? dbm 824?849 mhz wcdma ? ?11 ? dbm 880?915 mhz e-gsm ? ?10 ? dbm 880?915 mhz wcdma ? ?10 ? dbm 1710?1785 mhz gsm1800 ? ?16 ? dbm 1710?1785 mhz wcdma ? ?16 ? dbm 1850?1910 mhz gsm1900 ? ?17 ? dbm 1850?1910 mhz wcdma ? ?16 ? dbm 1880?1920 mhz td-scdma ? ?18 ? dbm table 28: bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 103 1920?1980 mhz wcdma ? ?17 ? dbm 2010?2025 mhz td-scdma ? ?19 ? dbm 2500?2570 mhz wcdma ? ?23 ? dbm 2500?2570 mhz d band 7 ? ?24.4 ? dbm 2300?2400 mhz e band 40 ? ?36.5 ? dbm 2570?2620 mhz f band 38 ? ?21 ? dbm 2545?2575 mhz g xgp band ? ?22 ? dbm 8-dpsk (3 mbps) c 698-716 mhz wcdma ? ?13 ? dbm 776-794 mhz wcdma ? ?13 ? dbm 824-849 mhz gsm850 ? ?13 ? dbm 824-849 mhz wcdma ? ?14 ? dbm 880-915 mhz e-gsm ? ?13 ? dbm 880-915 mhz wcdma ? ?13 ? dbm 1710-1785 mhz gsm1800 ? ?18 ? dbm 1710-1785 mhz wcdma ? ?17 ? dbm 1850-1910 mhz gsm1900 ? ?19 ? dbm 1850-1910 mhz wcdma ? ?19 ? dbm 1880-1920 mhz td-scdma ? ?19 ? dbm 1920-1980 mhz wcdma ? ?19 ? dbm 2010-2025 mhz td-scdma ? ?20 ? dbm 2500-2570 mhz wcdma ? ?23 ? dbm 2500?2570 mhz d band 7 ? ?24.7 ? dbm 2300?2400 mhz e band 40 ? ?36.7 ? dbm 2570?2620 mhz f band 38 ? ?21 ? dbm 2545?2575 mhz g xgp band ? ?22 ? dbm table 28: bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 104 spurious emissions 30 mhz?1 ghz ? ?95 ?62 dbm 1?12.75 ghz ? ?70 ?47 dbm 851?894 mhz ? ?147 ? dbm/hz 925?960 mhz ? ?147 ? dbm/hz 1805?1880 mhz ? ?147 ? dbm/hz 1930?1990 mhz ? ?147 ? dbm/hz 2110?2170 mhz ? ?147 ? dbm/hz a. dirty tx is off. b. the maximum value represents the actual bluetooth specification required for bluetooth qualification as defined in the version 4.1 specification. c. 3 db receiver desense. d. 2560 mhz performance is used. e. 2360 mhz performance is used. f. 2580 mhz performance is used. g. 2555 mhz performance is used. table 29: bluetooth transmitter rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the bluetooth chip port output, unless otherwise defined. general frequency range 2402 ? 2480 mhz basic rate (gfsk) tx power at bluetooth ? 12 ? dbm qpsk tx power at bluetooth ? 8 ? dbm 8psk tx power at bluetooth ? 8 ? dbm power control step ? 2 4 8 db note: output power is with tca and tssi enabled. gfsk in-band spurious emissions ?20 dbc bw ? ? 0.93 1 mhz edr in-band spurious emissions 1.0 mhz < |m ? n| < 1.5 mhz m ? n = the frequency range for which the spurious emission is measured relative to the transmit center frequency. ? ?38 ?26 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ?31 ?20 dbm |m ? n| ? 2.5 mhz a ? ?43 ?40 dbm table 28: bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 105 out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36 b, c dbm 1 ghz to 12.75 ghz ? ? ? ?30 b, d, e dbm 1.8 ghz to 1.9 ghz ? ? ? ?47 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47 dbm gps band spurious emissions spurious emissions ? ? ?103 ? dbm out-of-band noise floor f 65?108 mhz fm rx ? ?147 ? dbm/hz 776?794 mhz cdma2000 ? ?146 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?146 ? dbm/hz 925?960 mhz e-gsm ? ?146 ? dbm/hz 1570?1580 mhz gps ? ?146 ? dbm/hz 1805?1880 mhz gsm1800 ? ?144 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?143 ? dbm/hz 2110?2170 mhz wcdma ? ?137 ? dbm/hz 2500?2570 mhz band 7 ? ?130 ? dbm/hz 2300?2400 mhz band 40 ? ?130 ? dbm/hz 2570?2620 mhz band 38 ? ?132 ? dbm/hz 2545?2575 mhz xgp band ? ?135 ? dbm/hz a. the typical number is measured at 3 mhz offset. b. the maximum value represents the value required for bluetooth qualification as defined in the v4.1 specification. c. the spurious emissions during idle mode are the same as specified in table 29 on page 104 . d. specified at the bluetooth antenna port. e. meets this specification using a front-end band-pass filter. f. transmitted power in cellular and fm bands at the antenna port. see figure 32 on page 100 for location of the port. table 29: bluetooth transmitter rf specifications (cont.) parameter conditions minimum typical maximum unit bluetooth rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 106 table 30: local oscillator performance parameter minimum typical maximum unit lo performance lock time ? 72 ? ? s initial carrier frequency tolerance ? 25 75 khz frequency drift dh1 packet ? 8 25 khz dh3 packet ? 8 40 khz dh5 packet ? 8 40 khz drift rate ? 5 20 khz/50 s frequency deviation 00001111 sequence in payload a a. this pattern represents an average deviation in payload. 140 155 175 khz 10101010 sequence in payload b b. pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 115 140 ? khz channel spacing ? 1 ? mhz table 31: ble rf specifications parameter conditions minimum typical maximum unit frequency range ? 2402 ? 2480 mhz rx sense a a. dirty tx is off. gfsk, 0.1% ber, 1 mbps ? ?96.5 ? dbm tx power b b. the ble tx power cannot exceed 10 dbm eirp specification limit. the front-end losses and antenna gain/loss must be factored in so as not to exceed the limit. ? ? 8.5 ? dbm mod char: delta f1 average ? 225 255 275 khz mod char: delta f2 max. c c. at least 99.9% of all delta f2 max. frequency values recorded over 10 packets must be greater than 185 khz. ?230??% mod char: ratio ? 0.8 1 ? % fm receiver specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 107 section 16: fm receiver specifications unless otherwise stated, limit values apply for the conditions specified in table 25: ?environmental ratings,? on page 98 and table 27: ?recommended operating conditions and dc characteristics,? on page 99 . typical values apply for the following conditions: ? vbat = 3.6v ? ambient temperature +25c table 32: fm receiver specifications parameter conditions a minimum typical maximum units rf parameters operating frequency b frequencies inclusive 65 ? 108 mhz sensitivity c fm only snr > 26 db ??1? db v emf ?0.9? v emf ??7? db v receiver adjacent channel selectivity c, d measured for 30 db snr at the audio output with best tune. signal of interest: 23 db v emf (14.1 v emf), at 200 khz. ? 51 ? db at 400 khz ? 62 ? db intermediate signal plus noise-to-noise ratio (s+n)/n c vin = 20 db v emf (10 v emf) 45 53 ? db intermodulation performance c, d blocker level increased until desired at 30 db snr wanted signal: 33 db v emf (45 v emf) modulated interferer: at f wanted + 400 khz and + 4mhz cw interferer: at f wanted + 800 khz and + 8mhz ?55? dbc am suppression, mono c vin = 23 db v emf (14.1 v emf) am at 400 hz with m = 0.3 no a-weighted or any other filtering applied. 40 ? ? db rds rds sensitivity e, f rds deviation = 1.2 khz ? 16 ? db v emf ?6.3? v emf ?10? db v rds deviation = 2 khz ? 12 ? db v emf ?4? v emf ?6? db v fm receiver specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 108 rds selectivity f wanted signal: 33 db v emf (45 v emf), 2 khz rds deviation with best tune interferer: ? f = 40 khz, fmod = 1 khz 200 khz ? 49 ? db 300 khz ? 52 ? db 400 khz ? 52 ? db rf input impedance ? 1.5 ? ? k ? antenna tuning capacitor ? 2.5 ? 30 pf maximum input level c snr > 26 db ? ? 113 db v emf ??446mv emf ??107db v rf conducted emissions local oscillator breakthrough measured on the reference port ???55dbm 869?894 mhz, 925?960 mhz, 1805?1880 mhz, 1930?1990 mhz. gps ???90dbm rf blocking levels at the fm antenna input 40 db snr (assumes a 50 ? at the radio input and excludes spurs) gsm850, e-gsm (std), bw = 0.2 mhz, 824?849 mhz 880?915 mhz ?5? dbm gsm850, e-gsm (edge), bw = 0.2 mhz, 824?849 mhz 880?915 mhz ??4? dbm gsm dcs 1800, pcs 1900 (std/edge), bw = 0.2 mhz, 1710?1785 mhz 1850?1910 mhz ?12? dbm wcdma: ii(i), iii (iv, x), bw = 5 mhz, 1850?1980 mhz (1920?1980 mhz), 1710?1785 mhz (1710?1755 mhz, 1710?1770 mhz) ?12? dbm table 32: fm receiver specifications (cont.) parameter conditions a minimum typical maximum units fm receiver specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 109 ? wcdma: v(vi), viii, xii, xiii, xiv, bw = 5 mhz, 824?849 mhz (830?840 mhz), 880?915 mhz ?1? dbm cdma2000, cdmaone, bw = 1.25 mhz, 824?849 mhz, 887?925 mhz, 776?794 mhz ??3? dbm cdma2000, cdmaone, bw = 1.25 mhz, 1850?1910 mhz, 1750?1780 mhz, 1920?1980 mhz ?12? dbm bluetooth, bw = 1 mhz, 2402?2480 mhz ?11? dbm ieee 802.11g/b, bw = 20 mhz, 2400?2483.5 mhz ?11? dbm ieee 802.11a, bw = 20 mhz, 4915?5825 mhz ?6? dbm 2500?2570 mhz band 7 ? 11 ? dbm 2300?2400 mhz band 40 ? 11 ? dbm 2570?2620 mhz band 38 ? 11 ? dbm 2545?2575 mhz xgp band ? 11 ? dbm tuning frequency step ? 10 ? ? khz settling time single-frequency switch in any direction to a frequency within the bands 88? 108 mhz or 76?90 mhz. time measured to within 5 khz of the final frequency. ? 150 ? s search time total time for an automatic search to sweep from 88?108 mhz or 76?90 mhz (and reverse direction) assuming no channels are found. ??8 sec general audio audio output level g ? ?14.5 ? ?12.5 dbfs maximum audio output level h ???0dbfs audio dac output level g ?72?88mvrms maximum dac audio output level h ? ? 333 ? mvrms audio dac output level difference i ??1?1db table 32: fm receiver specifications (cont.) parameter conditions a minimum typical maximum units fm receiver specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 110 left and right ac mute fm input signal fully muted with dac enabled 60 ? ? db left and right hard mute fm input signal fully muted with dac disabled 80 ? ? db soft mute attenuation and start level muting is performed dynamically proportional to the fm wanted input signal c/n. the muting characteristic is fully programmable. refer to ?audio features? on page 62 for further details. ??? ? maximum signal plus noise-to-noise ratio (s + n)/n, mono i ??68?db maximum signal plus noise-to-noise ratio (s + n) n, stereo g ??64?db total harmonic distortion, mono vin = 66 db v emf (2 mv emf), ? f = 75 khz, fmod = 400 hz ??1.5% ? f = 75 khz, fmod = 1 khz ? ? ?60 % ? f = 75 khz, fmod = 3 khz ? ? 0.8 % ? f = 100 khz, fmod = 1 khz ? ? 1.0 % total harmonic distortion, stereo vin = 66 db v emf (2 mv emf) ? f = 67.5 khz, fmod = 1 khz, ? f pilot = 7.5 khz, l = r ??1.5% audio spurious products i range from 300 hz to 15 khz, with respect to 1 khz tone ???60dbc audio bandwidth, upper (?3 db point) vin = 66 db v emf (2 mv emf) ? f = 8 khz, for 50 s 15 ? ? khz audio bandwidth, lower (?3 db point) ??20hz audio in-band ripple 100 hz to 13 khz, vin = 66 db v emf (2 mv emf) ? f = 8 khz, for 50 s ?0.5 ? 0.5 db de-emphasis time constant tolerance with respect to 50 and 75 s ? ? 5 % rssi range with 1 db resolution and 5 db accuracy at room temp 3?83db v emf 1.41 ? 1.41e + 04 v emf ?3 ? 77 db v stereo decoder stereo channel separation forced stereo mode vin = 66 db v emf (2 mv emf), ? f = 67.5 khz, fmod = 1 khz, ? f pilot = 6.75 khz r = 0, l = 1 ?48? db table 32: fm receiver specifications (cont.) parameter conditions a minimum typical maximum units fm receiver specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 111 mono stereo blend and switching blending and switching is dynamically proportional to the fm wanted input signal c/n. the blending and switching characteristics are fully programmable. refer to ?audio features? on page 62 for further details. ? ?? ? pilot suppression vin = 66 db v emf (2 mv emf), ? f = 75 khz, fmod = 1 khz 46 ? ? db pause detection audio level at which a pause is detected relative to 1 khz tone, ? f = 22.5 khz ? ? ? ? four values in 3 db steps ?21 ? ?12 db audio pause duration four values 20 ? 40 ms a. following conditions are applied to all relevant tests unless otherwise indicated: pre-emphasis and de-emphasis of 50 us, r = l for mono, dac load > 20 k ? , baf = 300 hz to 15 khz, and a-weighted filtering applied. b. contact broadcom regarding applications that operate between 65 and 76 mhz. c. wanted signal: ? f = 22.5 khz, and fmod = 1 khz. d. interferer: ? f = 22.5 khz, and fmod = 1 khz. e. rds sensitivity numbers are for 87.5?108 mhz only. f. vin = ? f = 32 khz, fmod = 1 khz, ? f pilot = 7.5 khz, and 95% of blocks decoded with no errors after correction g. vin = 66 db v emf (2 mv emf), ? f = 22.5 khz, fmod = 1 khz, and ? f pilot = 6.75 khz. h. vin = 66 db v emf (2 mv emf), ? f = 100 khz, fmod = 1 khz, and ? f pilot = 6.75 khz. i. vin = 66 db v emf (2 mv emf), ? f = 22.5 khz, and fmod = 1 khz. table 32: fm receiver specifications (cont.) parameter conditions a minimum typical maximum units wlan rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 112 section 17: wlan rf specifications introduction the BCM43455 includes an integrated dual-band direct conversion radio that supports the 2.4 ghz and the 5 ghz bands. this section describes the rf characteristics of the 2.4 ghz and 5 ghz radio. unless otherwise stated, limit values apply for the conditions specified in table 25: ?environmental ratings,? on page 98 and table 27: ?recommended operating conditions and dc characteristics,? on page 99 . typical values apply for the following conditions: ? vbat = 3.6v ? ambient temperature +25c figure 33: port locations for wlan testing note: values in this section of the data sheet are design goals and are subject to change based on device characterization results. note: unless otherwise defined, all wlan specifications are provided at the chip port. optional filter bt pa 2g pa lna 5g lna 2g 5g pa diplexer chip port antenna port antenna port 2.4g configured with itr rf port optional filter bt pa 2g pa lna 5g lna 2g 5g pa diplexer rf port chip port 2.4g configured with etr chip port chip port chip port chip port chip port chip port rf port 2.4 ghz band general rf specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 113 2.4 ghz band genera l rf specifications wlan 2.4 ghz receiver pe rformance specifications table 33: 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s power-up and power-down ramp time dsss/cck modulations ? ? <2 s note: the specifications shown in the following table are provided at the chip port, unless otherwise defined. table 34: wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity ieee 802.11b (8% per for 1024 octet psdu) 1 mbps dsss ? ?98.7 ? dbm 2 mbps dsss ? ?96.0 ? dbm 5.5 mbps dsss ? ?94.4 ? dbm 11 mbps dsss ? ?90.7 ? dbm rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) 6 mbps ofdm ? ?95.3 ? dbm 9 mbps ofdm ? ?94.3 ? dbm 12 mbps ofdm ? ?93.5 ? dbm 18 mbps ofdm ? ?90.9 ? dbm 24 mbps ofdm ? ?87.7 ? dbm 36 mbps ofdm ? ?84.4 ? dbm 48 mbps ofdm ? ?79.6 ? dbm 54 mbps ofdm ? ?78.2 ? dbm rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94.8 ? dbm mcs1 ? ?92.3 ? dbm mcs2 ? ?89.8 ? dbm mcs3 ? ?86.4 ? dbm mcs4 ? ?83.3 ? dbm mcs5 ? ?78.6 ? dbm mcs6 ? ?76.7 ? dbm mcs7 ? ?74.7 ? dbm wlan 2.4 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 114 rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) b defined for default parameters: 800 ns gi and non-stbc 20 mhz channel spacing for all mcs rates mcs0 ? ?95.0 ? dbm mcs1 ? ?92.3 ? dbm mcs2 ? ?90.1 ? dbm mcs3 ? ?87.0 ? dbm mcs4 ? ?83.6 ? dbm mcs5 ? ?78.7 ? dbm mcs6 ? ?76.8 ? dbm mcs7 ? ?75.9 ? dbm mcs8 ? ?71.5 ? dbm rx sensitivity ieee 802.11ac with ldpc (10% per for 4096 octet psdu) at rf port. defined for default parameters: 800 ns gi, ldpc coding, and non- stbc. 20 mhz channel spacing for all mcs rates mcs7 ? ?77.8 ? dbm mcs8 ? ?74.0 ? dbm mcs9 ? ?72.0 ? dbm table 34: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 115 blocking level for 3 db rx sensitivity degradation (without external filtering) c 776?794 mhz (cdma2000): blocker frequency = 794 mhz ? ?16 ? dbm 824?849 mhz d (cdmaone): blocker frequency = 849 mhz ? ?11 ? dbm 824?849 mhz (gsm850): blocker frequency = 849 mhz ? ?11 ? dbm 880?915 mhz (e-gsm): blocker frequency = 915 mhz ? ?11 ? dbm 1710?1785 mhz (gsm1800): blocker frequency = 1785 mhz ? ?12 ? dbm 1850?1910 mhz (gsm1900): blocker frequency = 1910 mhz ? ?13 ? dbm 1850?1910 mhz (cdmaone): blocker frequency = 1910 mhz ? ?5 ? dbm 1850?1910 mhz (wcdma): blocker frequency = 1910 mhz ? ?19 ? dbm 1920?1980 mhz (wcdma): blocker frequency = 1980 mhz ? ?19 ? dbm 2300?2400 mhz (lte band 40) blocker frequency = 2300 mhz ? ?29 ? dbm blocker frequency = 2365 mhz ? ?35 ? dbm 2500?2570 mhz (lte band 7): blocker frequency = 2505 mhz ? ?39 ? dbm blocker frequency = 2565 mhz ? ?35 ? dbm 2570?2620 mhz (lte band 38): blocker frequency = 2575 mhz ? ?35 ? dbm 2496-2690 mhz (lte band 41): blocker frequency = 2501 mhz ? ?42 ? dbm blocker frequency = 2685 mhz ? ?17 ? dbm 2545?2575 mhz (xgp band): blocker frequency = 2550 mhz ? ?33 ? dbm in-band static cw jammer immunity (fc ? 8 mhz < fcw < + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsens + 23 db < rxlevel < max. input level) ?80 ? ? dbm input in-band ip3 maximum lna gain ? ?10 ? dbm minimum lna gain ? 15 ? dbm table 34: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 116 maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1024 octets) ?9.5 ? ? dbm @ mcs0?mcs7 rates (10% per, 4095 octets) ?9.5 ? ? dbm @ mcs8?mcs9 rates (10% per, 4095 octets) ?11.5 ? ? dbm adjacent channel rejection- dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection- ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db adjacent channel rejection mcs0?mcs9 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs0 ?79 dbm 16 ? ? db mcs1 ?76 dbm 13 ? ? db mcs2 ?74 dbm 11 ? ? db mcs3 ?71 dbm 8 ? ? db mcs4 ?67 dbm 4 ? ? db mcs5 ?63 dbm 0 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs7 ?61 dbm ?2 ? ? db mcs8 ?59 dbm ?4 ? ? db mcs9 ?57 dbm ?6 ? ? db maximum receiver gain ? ? ? 70 ? db gain control step ? ? ? 3 ? db rssi accuracy e range ?95 f dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? , across the dynamic range 10 11.5 13 db receiver cascaded noise figure at maximum gain ? 4 ? db table 34: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz transmitter performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 117 wlan 2.4 ghz transmitter performance specifications a. sensitivity degradations for alternate settings in mcs modes. sgi: 2 db drop. b. sensitivity degradations for alternate settings in mcs modes. sgi: 2 db drop. c. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. it is not intended to indicate any specific usage of each band in any specific country. d. the blocking levels are valid for channels 1 to 11. (for higher channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) e. the minimum and maximum values shown have a 95% confidence level. f. ?95 dbm with calibration at time of manufacture, ?92 dbm without calibration. note: unless otherwise noted, the values shown in the following table are provided at the wlan chip port output. table 35: wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and fm bands (at +21 dbm, 100% duty cycle, 1 mbps cck) a 776-794 mhz (cdma2000) ? ?164 ? dbm/hz 869?960 mhz (cdmaone, gsm850) ? ?163 ? dbm/hz 1450?1495 (dab) ? ?153.6 ? dbm/hz 1570?1580 mhz (gps) ? ?151.2 ? dbm/hz 1592?1610 mhz (glonass) ? ?150.4 ? dbm/hz 1710?1800 (dsc-1800-uplink) ? ?145 ? dbm/hz 1805?1880 mhz (gsm 1800) ? ?139 ? dbm/hz 1850?1910 mhz (gsm 1900) ? ?139 ? dbm/hz 1910?1930 mhz (tdscdma,lte) ? ?140 ? dbm/hz 1930?1990 mhz (gsm1900, cdmaone, wcdma) ? ?128 ? dbm/hz 2010?2075 mhz (tdscdma) ? ?131 ? dbm/hz 2110?2170 mhz (wcdma) ? ?125 ? dbm/hz 2305?2370 (lte band 40) ? ?95 ? dbm/hz 2370?2400 (lte band 40) ? ?80 ? dbm/hz 2496-2530 (lte band 41) ? ?90 ? dbm/hz 2530-2560 (lte band 41) ? ?110 ? dbm/hz 2570-2690 (lte band 41) ? ?116 ? dbm/hz 5000-5900 (wlan 5g) ? ?155 ? dbm/hz wlan 5 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 118 wlan 5 ghz receiver performance specifications evm does not exceed tx power at the chip port for highest power level setting at 25c and vbat = 3.6v with spectral mask and evm compliance 802.11b (dsss/cck) ?9 db ? 21.5 ? dbm ofdm, bpsk ?8 db ? 20 ? dbm ofdm, 64qam ?25 db ? 19 ? dbm mcs7 ?27 db ? 19 ? dbm mcs8 ?30 db ? 17 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.45 ? degrees tx power control dynamic range ?10??db closed-loop tx power variation at highest power level setting across full temperature and voltage range. applies to 10 dbm to 20 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss at chip port tx z o = 50 ? ?6?db a. the cellular standards listed indicate only typical usages of that band in some countries. other standards may also be used within those bands. note: unless otherwise noted, the values shown in the following table are provided at the chip port input. table 36: wlan 5 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz rx sensitivity a ieee 802.11a (10% per for 1000 octet psdu) 6 mbps ofdm ? ?94.5 ? dbm 9 mbps ofdm ? ?93.5 ? dbm 12 mbps ofdm ? ?92.7 ? dbm 18 mbps ofdm ? ?90.1 ? dbm 24 mbps ofdm ? ?86.9 ? dbm 36 mbps ofdm ? ?83.6 ? dbm 48 mbps ofdm ? ?78.6 ? dbm 54 mbps ofdm ? ?77.4 ? dbm table 35: wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 119 rx sensitivity a ieee 802.11n (10% per for 4096 octet psdu) defined for default parameters: 800 ns gi and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94.0 ? dbm mcs1 ? ?91.5 ? dbm mcs2 ? ?89.0 ? dbm mcs3 ? ?85.6 ? dbm mcs4 ? ?82.5 ? dbm mcs5 ? ?77.8 ? dbm mcs6 ? ?75.9 ? dbm mcs7 ? ?73.9 ? dbm rx sensitivity a ieee 802.11n (10% per for 4096 octet psdu) defined for default parameters: 800 ns gi and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?92.0 ? dbm mcs1 ? ?89.0 ? dbm mcs2 ? ?86.5 ? dbm mcs3 ? ?83.2 ? dbm mcs4 ? ?79.9 ? dbm mcs5 ? ?75.3 ? dbm mcs6 ? ?73.8 ? dbm mcs7 ? ?72.2 ? dbm rx sensitivity a ieee 802.11ac (10% per for 4096 octet psdu) defined for default parameters: 800 ns gi and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94.2 ? dbm mcs1 ? ?91.5 ? dbm mcs2 ? ?89.3 ? dbm mcs3 ? ?86.2 ? dbm mcs4 ? ?82.8 ? dbm mcs5 ? ?77.9 ? dbm mcs6 ? ?76.0 ? dbm mcs7 ? ?75.1 ? dbm mcs8 ? ?70.7 ? dbm rx sensitivity a ieee 802.11ac (10% per for 4096 octet psdu) defined for default parameters: 800 ns gi and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?92.3 ? dbm mcs1 ? ?89.3 ? dbm mcs2 ? ?86.9 ? dbm mcs3 ? ?83.6 ? dbm mcs4 ? ?80.2 ? dbm mcs5 ? ?75.6 ? dbm mcs6 ? ?74.0 ? dbm mcs7 ? ?72.6 ? dbm mcs8 ? ?68.3 ? dbm mcs9 ? ?66.7 ? dbm table 36: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 120 rx sensitivity a ieee 802.11ac (10% per for 4096 octet psdu) defined for default parameters: 800 ns gi and non-stbc. 80 mhz channel spacing for all mcs rates mcs0 ? ?89.0 ? dbm mcs1 ? ?86.0 ? dbm mcs2 ? ?83.3 ? dbm mcs3 ? ?80.1 ? dbm mcs4 ? ?76.8 ? dbm mcs5 ? ?72.2 ? dbm mcs6 ? ?70.9 ? dbm mcs7 ? ?69.2 ? dbm mcs8 ? ?65.2 ? dbm mcs9 ? ?63.6 ? dbm rx sensitivity a ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) at rf port. defined for default parameters: 800 ns gi, ldpc coding and non- stbc. mcs7 20 mhz ? ?76.8 ? dbm mcs8 20 mhz ? ?72.9 ? dbm mcs9 20 mhz ? ?70.7 ? dbm mcs7 40 mhz ? ?74.8 ? dbm mcs8 40 mhz ? ?70.9 ? dbm mcs9 40 mhz ? ?68.9 ? dbm mcs7 80 mhz ? ?71.5 ? dbm mcs8 80 mhz ? ?67.6 ? dbm mcs9 80 mhz ? ?65.5 ? dbm table 36: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 121 blocking level for 3 db rx sensitivity degradation (without external filtering) b 776?794 mhz (cdma2000): blocker frequency = 794 mhz ??21? dbm 824?849 mhz c (cdmaone): blocker frequency = 849 mhz ??20? dbm 824?849 mhz (gsm850): blocker frequency = 849 mhz ??10? dbm 880?915 mhz (e-gsm): blocker frequency = 915 mhz ??12? dbm 1710?1785 mhz (gsm1800): blocker frequency = 1785 mhz ??13? dbm 1850?1910 mhz (gsm1900): blocker frequency = 1910 mhz ??13? dbm 1850?1910 mhz (cdmaone): blocker frequency = 1910 mhz ??18? dbm 1850?1910 mhz (wcdma): blocker frequency = 1910 mhz ??20? dbm 1920?1980 mhz (wcdma): blocker frequency = 1980 mhz ??20? dbm 2300?2400 mhz (lte band 40) blocker frequency = 2395 mhz ??19? dbm 2500?2570 mhz (lte band 7): blocker frequency = 2565 mhz ??16? dbm 2570?2620 mhz (lte band 38): blocker frequency = 2615 mhz ??16? dbm 2496-2690 mhz (lte band 41): blocker frequency = 2685 mhz ??16? dbm 2545?2575 mhz (xgp band): blocker frequency = 2570 mhz ??18? dbm table 36: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 122 input in-band ip3 maximum lna gain ? ?11 ? dbm minimum lna gain ? 5 ? dbm maximum receive level @ 5.24 ghz @ 6, 9, 12 mbps ?9.5 ? ? dbm @ 18, 24, 36, 48, 54 mbps ?14.5 ? ? dbm adjacent channel rejection (difference between interfering and desired signal (20 mhz apart) at 10% per for 1000 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db alternate adjacent channel rejection (difference between interfering and desired signal (40 mhz apart) at 10% per for 1000 d octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?78.5 dbm 32 ? ? db 9 mbps ofdm ?77.5 dbm 31 ? ? db 12 mbps ofdm ?75.5 dbm 29 ? ? db 18 mbps ofdm ?73.5 dbm 27 ? ? db 24 mbps ofdm ?70.5 dbm 24 ? ? db 36 mbps ofdm ?66.5 dbm 20 ? ? db 48 mbps ofdm ?62.5 dbm 16 ? ? db 54 mbps ofdm ?61.5 dbm 15 ? ? db 65 mbps ofdm ?60.5 dbm 14 ? ? db maximum receiver gain ? ? 65 ? db gain control step ? ? 3 ? db table 36: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz receiver performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 123 rssi accuracy e range ?98 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? , across the dynamic range 10 ? 13 db receiver cascaded noise figure at maximum gain ? 4 ? db a. for pcie derate 5g rx sensitivity by 1.5 db b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. it is not intended to indicate any specific usage of each band in any specific country. c. the blocking levels are valid for channels 1 to 11. (for higher channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) d. for 65 mbps, the size is 4096. e. the minimum and maximum values shown have a 95% confidence level. table 36: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz transmitter performance specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 124 wlan 5 ghz transmitter performance specifications note: unless otherwise noted, the values shown in the following table are provided at the wlan chip port output. table 37: wlan 5 ghz transmitter performance specifications parameter condition/notes minimum typical maximu m unit frequency range ? 4900 ? 5845 mhz transmitted power in cellular and fm bands (at +18.5 dbm, 100% duty cycle, 6 mbps ofdm) a 776?794 mhz (cdma2000) ? ?164 ? dbm/hz 869?960 mhz (cdmaone, gsm850) ? ?166 ? dbm/hz 1450?1495 (dab) ? ?166 ? dbm/hz 1570?1580 mhz (gps) ? ?166 ? dbm/hz 1592?1610 mhz (glonass) ? ?165.5 ? dbm/hz 1710?1800(dsc-1800-uplink) ? ?135 ? dbm/hz 1805?1880 mhz (gsm 1800) ? ?165 ? dbm/hz 1850?1910 mhz (gsm 1900) ? ?165 ? dbm/hz 1910?1930 mhz (tdscdma, lte) ? ?165 ? dbm/hz 1930?1990 mhz (gsm1900, cdmaone, wcdma) ??165?dbm/hz 2010?2075 mhz (tdscdma) ? ?164.5 ? dbm/hz 2110?2170 mhz (wcdma) ? ?164 ? dbm/hz 2305?2370 (lte band 40) ? ?160 ? dbm/hz 2370?2400 (lte band 40) ? ?163 ? dbm/hz 2400?2500 (wlan 2g) ? ?160 ? dbm/hz 2496?2530 (lte band 41) ? ?161.5 ? dbm/hz 2530?2560 (lte band 41) ? ?161.5 ? dbm/hz 2570?2690 (lte band 41) ? ?161 ? dbm/hz evm does not exceed tx power at the chip port for highest power level setting at 25c and vbat = 3.6v with spectral mask and evm compliance ofdm, bpsk ?8 db ? 21.5 ? dbm ofdm, 64qam ?25 db ? 19 ? dbm mcs7 ?27 db ? 19 ? dbm mcs9 ?32 db ? 17 ? dbm general spurious emissions specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 125 general spurious emi ssions specifications this section provides the tx and rx spurious emissions specifications for both the wlan 2.4 ghz and 5 ghz bands. the recommended spectrum analyzer settings for the spurious emissions specifications are provided in ta b l e 3 8 . transmitter spurious emissions specifications the tx spurious emissions specifications in this subsection are based on the following definitions: ? afe = vco/16 for 2g channels ? afe = vco/18 for 5g 20 mhz channels ? afe = vco/9 for 5g 40 mhz channels ? afe = vco/6 for 5g 80 mhz channels ? lo = channel frequency phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.5 ? degrees tx power control dynamic range ?10??db closed loop tx power variation at highest power level setting across full-temperature and voltage range. applies across 10 to 20 dbm output power range. ??2.0db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss z o = 50 ? ?6?db a. the cellular standards listed indicate only typical usages of that band in some countries. other standards may also be used within those bands. table 38: recommended spectrum analyzer settings parameter setting resolution bandwidth (rbw): 1 mhz video bandwidth (vbw): 1 mhz sweep: auto span: 100 mhz detector: maximum peak trace: maximum hold modulation: ofdm (orthogonal frequency-division multiplexing) table 37: wlan 5 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximu m unit general spurious emissions specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 126 2.4 ghz band spurious emissions 20 mhz channel spacing note: possible afe combinations are as follows. the afe=vco/16 specifications for channel 2442 are listed in ta b l e 3 9 . table 39: 2.4 ghz band, 20 mhz channel spacing tx spurious emissions specifications a a. vco = 1.5 fch, where fch is the center frequency of the channel. spurious frequency power (dbm) frequency (fch; mhz) channel 2442 typical (dbm) maximum (dbm) hd2 21 ?22.78 ? hd3 21 ?19.54 ? hd4 21 ?41.79 ? hd5 21 ?61.78 ? vco ? lo 21 ?55.13 ? vco + lo 21 ?63.40 ? vco 21 ?48.56 ? lo + afe 21 ?59.2 ? lo-afe 21 ?59.3 ? lo + afe 2 21 ?68.2 ? lo ? afe 2 21 ?67.4 ? lo + xtal 2 21 ?56.2 ? lo ? xtal 2 21 ?56.3 ? lo + xtal 4 21 ?57.5 ? lo ? xtal 4 21 ?56.7 ? lo + xtal 8 21 ?59.1 ? lo ? xtal 8 21 ?67.2 ? general spurious emissions specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 127 5 ghz band spurious emissions 20 mhz channel spacing note: possible afe combinations are as follows. the afe=vco/18 specifications for channels 5180, 5500, and 5825 are listed in ta b l e 4 0 . table 40: 5 ghz band, 20 mhz channel sp acing tx spurious emissions specifications spurious frequency power (dbm) ch5180 a a. vco = (2/3) fch, where fch is the center frequency of the channel. ch5500 a ch5825 a typ. (dbm) max. (dbm) typ. (dbm) max. (dbm) typ. (dbm) max. (dbm) hd2 19 ?29.33 ? ?32.56 ? ?33.14 ? hd3 19 ?39.71 ? ?38.93 ? ?39.87 ? vco 19 ?49.03 ? ?48.35 ? ?46.70 ? vco 2 19 ?55.64 ? ?60.40 ? ?64.77 ? lo + vco 19 ?63.94 ? ?62.80 ? ?62.16 ? lo ? vco 19 ?81.58 ? ?72.56 ? ?70.58 ? lo ? afe 19 ?62.1 ? ?63.3 ? ?60.4 ? lo + afe 19 ?57.8 ? ?59.6 ? ?60.6 ? lo ? xtal 4 19 ?60.1 ? ?60.1 ? ?58.7 ? lo + xtal 4 19 ?57.2 ? ?57.4 ? ?58.2 ? lo ? xtal 6 19 ?63.4 ? ?59.3 ? ?61.1 ? lo + xtal 6 19 ?60.2 ? ?58.9 ? ?60.8 ? lo ? xtal 8 19 ?66.1 ? ?67.3 ? ?63.8 ? lo + xtal 8 19 ?64.2 ? ?63.8 ? ?65.8 ? afe 1219?????? general spurious emissions specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 128 40 mhz channel spacing note: possible afe combinations are as follows. the afe=vco/9 specifications for channels 5190, 5510, and 5795 are listed in ta b l e 4 1 . table 41: 5 ghz band, 40 mhz channel spacing tx spurious emissions specifications spurious frequency power (dbm) ch5190m a a. vco = (2/3) fch, where fch is the center frequency of the channel. ch5510m a ch5795m a typ. (dbm) max. (dbm) typ. (dbm) max. (dbm) typ. (dbm) max. (dbm) hd2 19 ?33.43 ? ?35.53 ? ?36.49 ? hd3 19 ?41.81 ? ?42.13 ? ?42.33 ? vco 19 ?48.36 ? ?47.65 ? ?46.93 ? vco 2 19 ?55.87 ? ?59.26 ? ?64.45 ? lo + vco 19 ?65.58 ? ?64.96 ? ? ? lo ? vco19?????? lo ? afe 19 ?65.3 ? ?67.2 ? ?65.2 ? lo + afe 19 ?63.2 ? ?64.3 ? ?67.3 ? lo ? xtal 4 19 ?59.3 ? ?59.7 ? ?59.6 ? lo + xtal 4 19 ?58.3 ? ?57.4 ? ?57.9 ? lo ? xtal 6 19 ?64.1 ? ?63.4 ? ?63.2 ? lo + xtal 6 19 ?61.5 ? ?59.4 ? ?61.2 ? lo ? xtal 8 19 ?66.3 ? ?67.1 ? ?64.3 ? lo + xtal 8 19 ?63.8 ? ?64.7 ? ?61.2 ? afe 12 19 ?65.2 ? ?66.3 ? ?65.4 ? general spurious emissions specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 129 80 mhz channel spacing receiver spurious emissions specifications note: possible afe combinations are as follows. the afe=vco/6 specifications for channels 5210, 5530, and 5775 are listed in ta b l e 4 2 . table 42: 5 ghz band, 80 mhz channel spacing tx spurious emissions specifications spurious frequency power (dbm) ch5210q a a. vco = (2/3) fch, where fch is the center frequency of the channel. ch5530q a ch5775q a typ. (dbm) max. (dbm) typ. (dbm) max. (dbm) typ. (dbm) max. (dbm) hd2 19 ?36.28 ? ?39.59 ? ?41.02 ? hd3 19 ?45.00 ? ?44.82 ? ?46.10 ? vco 19 ?48.00 ? ?47.34 ? ?46.01 ? vco 2 19 ?57.04 ? ?62.82 ? ?66.84 ? lo + vco 19 ?66.66 ? ?66.11 ? ?66.40 ? lo ? vco 19 ? ?? ?? ? lo ? afe 19 ?68.5 ? ?67.8 ? ?66.9 ? lo + afe 19 ?63.8 ? ?66.3 ? ?68.6 ? lo ? xtal 4 19 ? ?? ?? ? lo + xtal 4 19 ? ? ? ? ? ? lo ? xtal 6 19 ? ?? ?? ? lo + xtal 6 19 ? ? ? ? ? ? lo ? xtal 8 19 ? ?? ?? ? lo + xtal 8 19 ? ? ? ? ? ? afe 12 19 ? ? ? ? ? ? table 43: 2g and 5g general receiver spurious emissions band frequency range typical maximum unit 2g 2.4 ghz < f < 2.5 ghz ?92 ? dbm 3.6 ghz < f < 3.8 ghz ?75.16 ? dbm 5g 5150 mhz < f < 5850 mhz ?70.4 ? dbm 3.45 ghz < f < 3.9 ghz ?59.2 ? dbm internal regulator electrical specifications BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 130 section 18: internal regulator electrical specifications core buck switching regulator note: values in this data sheet are design goals and are subject to change based on device characterization results. note: functional operation is not guaranteed outside of the specification limits provided in this section. table 44: core buck switching regulator (cbuck) specifications specification notes min. typ. max. unit input supply voltage (dc) dc voltage range inclusive of disturbances. 3.0 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v ?4?mhz pwm output current ? ? ? 600 ma output current limit ? ? 1400 ? ma output voltage range programmable, 30 mv steps. default = 1.35v 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode. ?4?4% pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load. max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200 ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load 78 86 ? % pfm mode efficiency 10 ma load current 70 80 ? % start-up time from power down vio already on and steady. time from reg_on rising edge to cldo reaching 1.2v. ? 400 500 s external inductor 0806 size, 2.2 h, dcr=0.11 ? , acr=1.18 ? @ 4mhz ?2.2? h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 4.7 f 20%, 6.3v 2.0 4.7 10 b b. total capacitance includes those connected at the far end of the active load. f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 4.7uf 20%, 6.3v 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s 3.3v ldo (ldo3p3) BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 131 3.3v ldo (ldo3p3) table 45: ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 3.0 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v output current ? 0.001 ? 450 ma nominal output voltage, v o default = 3.3v ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? ? 100 a line regulation v in from (v o + 0.2v) to 5.25v, max. load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.3 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20??db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 1.0 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 f external input capacitor for sr_vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30m-200 m ? ), 10%, 10v. not needed if sharing vbat capacitor 4.7 f with sr_vddbatp5v. ?4.7? f 2.5v ldo (btldo2p5) BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 132 2.5v ldo (btldo2p5) table 46: btldo2p5 specifications specification notes min. typ. max. units input supply voltage min. = 2.5v + 0.2v = 2.7v. dropout voltage requirement must be met under maximum load for performance specifications. 3.0 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v nominal output voltage default = 2.5v. ? 2.5 ? v output voltage programmability range 2.2 2.5 2.8 v accuracy at any step (including line/ load regulation), load > 0.1 ma. ?5?5% dropout voltage at maximum load. ? ? 200 mv output current ? 0.1 ? 70 ma quiescent current no load. ? 8 16 a maximum load at 70 ma. ? 660 700 a leakage current power-down mode. ? 1.5 5 a line regulation v in from (v o + 0.2v) to 5.25v, maximum load. ??3.5mv/v load regulation load from 1 ma to 70 ma, v in = 3.6v. ??0.3mv/ma psrr v in v o + 0.2v, v o = 2.5v, c o = 2.2 f, maximum load, 100 hz to 100 khz. 20??db ldo turn-on time chip already powered up. ? ? 150 s in-rush current v in = v o + 0.15v to 5.25v, c o = 2.2 f, no load. ? ? 250 ma external output capacitor, c o ceramic, x5r, 0402, (esr: 5m?240 m ? ), 10%, 10v 0.7 b b. the minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, dc- bias, temperature, and aging. 2.2 2.64 f external input capacitor for sr_vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30?200 m ? ), 10%, 10v. not needed if sharing vbat 4.7 f capacitor with sr_vddbatp5v. ?4.7? f cldo BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 133 cldo table 47: cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.2 ? 200 ma output voltage, v o programmable in 10 mv steps. default = 1.2.v 0.95 1.2 1.26 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 13 ? a 200 ma load ? 1.24 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load ? ? 5 mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? 5 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20??db start-up time of pmu vio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ??700 s ldo turn-on time ldo turn-on time when rest of the chip is up ? 140 180 s external output capacitor, c o total esr: 5 m ? ?240 m ? 1.1 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2 f lnldo BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 134 lnldo table 48: lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. v in = v o + 0.15v = 1.35v (where v o = 1.2v)dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 44 ? a max. load ? 970 990 a line regulation v in from (v o + 0.1v) to 1.5v, 150 ma load ? ? 5 mv/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 mv/ma leakage current power-down ? ? 10 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ?12.2 f pcie ldo BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 135 pcie ldo table 49: pcie ldo specifications specification notes min. typ. max. units input supply voltage, vin min. v in = v o + 0.15v = 1.35v (where v o = 1.2v)dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current peak load=80 ma. average load=35 ma 0.1 ? 55 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 10 12 a 55 ma load ? 550 570 a line regulation v in from (v o + 0.1v) to 1.5v, 150 ma load ? ? 5 mv/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 mv/ma leakage current power-down ? 5 20 a bypass mode ? 0.02 1.5 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ?? 60 35 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v 20 ? ? db ldo turn-on time ldo turn-on time when balance of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.27 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 0.47 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ?12.2 f system power consumption BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 136 section 19: system power consumption wlan current consumption the tables in this subsection show the typical, total current consumed by the BCM43455. all values shown are with the bluetooth core in reset mode with bluetooth off. 2.4 ghz mode note: values in this data sheet are design goals and are subject to change based on the results of device characterization. note: unless otherwise stated, these values apply for the conditions specified in table 27: ?recommended operating conditions and dc characteristics,? on page 99 . table 50: 2.4 ghz mode wlan power consumption mode v bat = 3.6v, v ddio = 1.8v, t a 25c v bat, ma v io, ua a sleep modes radio off b 0.006 5 sleep c 0.020 200 ieee power save: dtim = 1, single rx d 1.25 200 ieee power save: dtim = 3, single rx 0.45 200 active rx modes continuous rx mode: mcs7, ht20, 1ss e, f 55 60 crs: ht20 g 50 60 wlan current consumption BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 137 5 ghz mode active tx modes ? internal pa continuous tx mode: 1 mbps @ 21.5 dbm h 400 60 continuous tx mode: mcs7, ht20, 1ss, 1 tx @ 19 dbm h 350 60 a. vio is specified with all pins idle (not switching) and not driving any loads. b. wl_reg_on and bt_reg_on are both low. all supplies are present. c. idle, not associated, or inter-beacon. d. beacon interval = 102.4 ms. beacon duration = 1 ms @ 1 mbps. average current over 3 dtim intervals. e. duty cycle is 100%. carrier sense (cs) detect/packet receive. f. measured using packet engine test mode. g. carrier sense (cca) when no carrier present. h. duty cycle is 100%. table 51: 5 ghz mode wlan power consumption mode v bat = 3.6v, v ddio = 1.8v, t a 25c v bat , ma v io, ua a sleep modes radio off b 0.006 5 sleep c 0.025 200 ieee power save: dtim = 1, single rx d 1.1 200 ieee power save: dtim = 3, single rx 0.4 200 active rx modes continuous rx mode: mcs7, ht20, 1ss e, f 74 60 continuous rx mode: mcs7, ht40, 1ss e, f 82 60 continuous rx mode: mcs9, ht40, 1ss e, f 86 60 continuous rx mode: mcs9, ht80, 1ss e, f 117 60 crs: ht20 g 70 60 crs: ht40 g 79 60 crs: ht80 g 100 60 active tx modes ? internal pa continuous tx mode: mcs7, ht20, 1ss, 1 tx @ 19 dbm h 330 60 continuous tx mode: mcs7, ht40, 1ss, 1 tx @ 19 dbm h 340 60 continuous tx mode: mcs9, ht40, 1ss, 1 tx @ 16 dbm h 270 60 continuous tx mode: mcs9, ht80, 1ss, 1 tx @ 16 dbm h 270 60 table 50: 2.4 ghz mode wlan power consumption (cont.) mode v bat = 3.6v, v ddio = 1.8v, t a 25c v bat, ma v io, ua a bluetooth current consumption BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 138 bluetooth current consumption the bluetooth and ble current consumption measurements are shown in table 52 . a. v io is specified with all pins idle (not switching) and not driving any loads. b. wl_reg_on and bt_reg_on are both low. all supplies present. c. idle, not associated, or inter-beacon. d. beacon interval = 102.4 ms. beacon duration = 1ms @ 1mbps. average current over 3x dtim intervals. e. duty cycle is 100%. carrier sense (cs) detect/packet receive. f. measured using packet engine test mode. g. carrier sense (cca) when no carrier present. h. duty cycle is 100%. note: the wlan core is in reset (wlan_reg_on = low) for all measurements provided in ta b le 5 2 . note: the bt current consumption numbers are measured based on gfsk tx output power = 10 dbm. table 52: bluetooth and ble current consumption operating mode vbat vddio units sleep 6 295 a standard 1.28s inquiry scan 153 294 a 500 ms sniff master 216 291 a dm1/dh1 master 23.9 0.155 ma dm3/dh3 master 29.1 0.164 ma dm5/dh5 master 29.8 0.166 ma 3dh5/3dh1 master 24.8 0.210 ma sco hv3 master 11.5 0.166 ma ble scan a a. no devices present. a 1.28 second interval with a scan window of 11.25 ms. 179 296 a ble adv?unconnectable 1.00 sec 69 295 a ble connected 1 sec 1960 146 a interface timing and ac characteristics BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 139 section 20: interface timing and ac characteristics sdio timing sdio default mode timing sdio default mode timing is shown by the combination of figure 34 and ta b l e 5 3 . figure 34: sdio bus timing (default mode) table 53: sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) frequency ? data transfer mode fpp 0 ? 25 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock low time tthl ? ? 10 ns t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 140 inputs: cmd, dat (referenced to clk) input setup time tisu5??ns input hold time tih5??ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly 0 ? 14 ns output delay time ? identification mode todly 0 ? 50 ns a. timing is based on cl ? 40 pf load on cmd and data. b. min (vih) = 0.7 vddio and max (vil) = 0.2 vddio. table 53: sdio bus timing a parameters (default mode) (cont.) parameter symbol minimum typical maximum unit sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 141 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 35 and ta b l e 5 4 . figure 35: sdio bus timing (high-speed mode) table 54: sdio bus timing a parameters (high-speed mode) a. timing is based on cl ? 40 pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl7??ns clock high time twh7??ns clock rise time ttlh??3ns clock low time tthl??3ns inputs: cmd, dat (referenced to clk) ????? input setup time tisu6??ns input hold time tih2??ns outputs: cmd, dat (referenced to clk) ????? output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 142 sdio bus timing specif ications in sdr modes clock timing figure 36: sdio clock timing (sdr modes) table 55: sdio bus clock timing parameters (sdr modes) parameter symbol minimum maximum unit comments ?t clk 40 ? ns sdr12 mode 20 ? ns sdr25 mode 10 ? ns sdr50 mode 4.8 ? ns sdr104 mode ?t cr , t cf ?0.2 t clk ns t cr , t cf < 2.00 ns (max) @ 100 mhz, c card = 10 pf t cr , t cf < 0.96 ns (max) @ 208 mhz, c card = 10 pf clock duty cycle ? 3070%? t clk t cr sdio_clk t cf t cr sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 143 card input timing figure 37: sdio bus input timing (sdr modes) table 56: sdio bus input timing parameters (sdr modes) symbol minimum maximum unit comments sdr104 mode t is 1.4 ? ns c card = 10 pf, vct = 0.975v t ih 0.8 ? ns c card = 5 pf, vct = 0.975v sdr50 mode t is 3.00 ? ns c card = 10 pf, vct = 0.975v t ih 0.8 ? ns c card = 5 pf, vct = 0.975v t is sdio_clk t ih cmd input dat[3:0] input sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 144 card output timing figure 38: sdio bus output timing (sdr modes up to 100 mhz) figure 39: sdio bus output timing (sdr modes 100 mhz to 208 mhz) table 57: sdio bus output timing parameters (sdr modes up to 100 mhz) symbol minimum maximum unit comments t odly ?7.5nst clk 10 ns c l = 30 pf using driver type b for sdr50 t odly ? 14.0 ns t clk 20 ns c l = 40 pf using for sdr12, sdr25 t oh 1.5 ? ns hold time at the t odly (min) c l = 15 pf t odly sdio_clk t oh cmd input dat[3:0] input t clk t op sdio_clk cmd input dat[3:0] input t clk t odw sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 145 ? ? t op = +1550 ps for junction temperature of ? t op = 90c during operation. ? ? t op = ?350 ps for junction temperature of ? t op = ?20c during operation. ? ? t op = +2600 ps for junction temperature of ? t op = ?20c to +125c during operation. figure 40: ? t op consideration for variable data window (sdr 104 mode) table 58: sdio bus output timing parameters (sdr modes 100 mhz to 208 mhz) symbol minimum maximum unit comments t op 0 2 ui card output phase ? t op ?350 +1550 ps delay variation due to temp change after tuning t odw 0.60 ? ui t odw = 2.88 ns @ 208 mhz ? t op = 1550 ps sampling point after tuning ? t op = ?350 ps data valid window data valid window data valid window sampling point after card junction heating by +90c from tuning temperature sampling point after card junction cooling by ?20c from tuning temperature sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 146 sdio bus timing specifications in ddr50 mode figure 41: sdio clock timing (ddr50 mode) table 59: sdio bus clock timing parameters (ddr50 mode) parameter symbol minimum maximum unit comments ?t clk 20 ? ns ddr50 mode ?t cr ,t cf ? 0.2 tclk ns t cr , t cf < 4.00 ns (max) @50 mhz, c card = 10 pf clock duty cycle ?45 55 %? t clk t cr sdio_clk t cf t cr sdio timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 147 data timing figure 42: sdio data timing (ddr50 mode) table 60: sdio bus timing parameters (ddr50 mode) parameter symbol minimum maximum unit comments input cmd input setup time t isu 6?nsc card < 10 pf (1 card) input hold time t ih 0.8 ? ns c card < 10 pf (1 card) output cmd output delay time t odly ?13.7nsc card < 30 pf (1 card) output hold time t oh 1.5 ? ns c card < 15 pf (1 card) input dat input setup time t isu2x 3?nsc card < 10 pf (1 card) input hold time t ih2x 0.8 ? ns c card < 10 pf (1 card) output dat output delay time t odly2x ?7.5nsc card < 25 pf (1 card) output hold time t odly2x 1.5 ? ns c card < 15 pf (1 card) t isu2x sdio_clk dat[3:0] input f pp t ih2x t isu2x t ih2x invalid invalid invalid invalid data data data data data data t odly2x (min) t odly2x (min) t odly2x (max) t odly2x (max) dat[3:0] output in ddr50 mode, dat[3:0] lines are sampled on both edges of the clock (not applicable for cmd line) available timing window for card output transition available timing window for host to sample data from card pci express interface parameters BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 148 pci express interface parameters table 61: pci express interface parameters parameter symbol comments minimum typical maximum unit general baud rate bps ? ? 5 ? gbau d reference clock amplitude vref lvpecl, ac coupled 1 ? ? v receiver differential termination zrx-diff-dc differential termination 80 100 120 ? dc impedance zrx-dc dc common-mode impedance 40 50 60 ? powered down termination (pos) zrx-high-imp-dc- pos power-down or reset high impedance 100k ? ? ? powered down termination (neg) zrx-high-imp-dc- neg power-down or reset high impedance 1k ? ? ? input voltage vrx-diffp-p ac coupled, differential p-p 175 ? ? mv jitter tolerance trx-eye minimum receiver eye width 0.4 ? ? ui differential return loss rlrx-diff differential return loss 10 ? ? db common-mode return loss rlrx-cm common-mode return loss 6??db unexpected electrical idle enter detect threshold integration time trx-idel-det-diff- entertime an unexpected electrical idle must be recognized no longer than this time to signal an unexpected idle condition. ??10ms signal detect threshold vrx-idle-det- diffp-p electrical idle detect threshold 65 ? 175 mv transmitter output voltage vtx-diffp-p differential p-p, programmable in 16 steps 0.8 ? 1200 mv output voltage rise time vtx-rise 20% to 80% 0.125 (2.5 gt/s) 0.15 (5 gt/s) ?? ui output voltage fall time vtx-fall 80% to 20% 0.125 (2.5 gt/s) 0.15 (5 gt/s) ?? ui pci express interface parameters BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 149 rx detection voltage swing vtx-rcv-detect the amount of voltage change allowed during receiver detection. ? ? 600 mv tx ac peak common- mode voltage (5 gt/s) vtx-cm-ac-pp tx ac common mode voltage (5 gt/s) ? ? 100 mv tx ac peak common- mode voltage (2.5 gt/s) vtx-cm-ac-p tx ac common mode voltage (2.5 gt/s) ??20mv absolute delta of dc common-model voltage during l0 and electrical idle vtx-cm-dc-active- idle-delta absolute delta of dc common-model voltage during l0 and electrical idle. 0 ? 100 mv absolute delta of dc common-model voltage between d+ and d- vtx-cm-dc-line- delta dc offset between d+ and d- 0?25mv electrical idle differential peak output voltage vtx-idle-diff-ac-p peak-to-peak voltage 0 ? 20 mv tx short circuit current itx-short current limit when tx output is shorted to ground. ??90ma dc differential tx termination ztx-diff-dc low impedance defined during signaling (parameter is captured for 5.0 ghz by rltx- diff) 80 ? 120 ? differential return loss rltx-diff differential return loss 10 (min.) for 0.05: 1.25 ghz 8 (min.) for 1.25: 2.5 ghz ?? db common-mode return loss rltx-cm common-mode return loss 6??db tx eye width ttx-eye minimum tx eye width 0.75 ? ? ui table 61: pci express interface parameters (cont.) parameter symbol comments minimum typical maximum unit jtag timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 150 jtag timing swd timing the probe outputs data to swdio on the falling edge of swdclk and captures data from swdio on the rising edge of swdclk. the target outputs data to swdio on the rising edge of swdclk and captures data from swdio on the rising edge of swdclk. swd timing is defined through the combination of figure 43 and ta b l e 6 3 . figure 43: swd read and write timing table 62: jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ? table 63: swd read and write timing parameters parameter description min. max. units tcyc swdclk cycle time 125 ? ns thigh swdclk high period 50 ? ns tlow swdclk low period 50 ? ns t os swdio output skew to the falling edge of swdclk ?5 5 ns t is input setup time between swdio and the rising edge of swdclk 20 ? ns t ih input hold time between swdio and the rising edge of swdclk 0 100 ns stop park acknowledge parity start data data tri-state thigh tlow t r i - s t a t e tri-state t os stop park acknowledge start tri-state t r i - s t a t e tri-state rvi probe output to swdio rvi probe output to swdclk target output to swdio parity data data rvi probe output to swdio rvi probe output to swdclk target output to swdio t ih t is write cycle read cycle power-up sequence and timing BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 151 section 21: power-up sequence and timing sequencing of reset and regulator control signals the BCM43455 has two signals that allow the host to control power consumption by enabling or disabling the bluetooth, wlan, and internal regulator blocks. these signals are described below. additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see figure 44 , figure 45 on page 152 , and figure 46 on page 153 and figure 47 on page 153 ). the timing values indicated are minimum required values; longer delays are also acceptable. description of control signals ? wl_reg_on : used by the pmu to power-up the wlan section. it is also or-gated with the bt_reg_on input to control the internal BCM43455 regulators. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low the wlan section is in reset. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. ? bt_reg_on : used by the pmu (or-gated with wl_reg_on) to power-up the internal BCM43455 regulators. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. when this pin is low and wl_reg_on is high, the bt section is in reset. note: for both the wl_reg_on and bt_reg_on pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). this is to allow time for the cbuck regulator to discharge. if this delay is not followed, then there may be a vddio in-rush current on the order of 36 ma during the next pmu cold start. note: the BCM43455 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold. wait at least 150 ms after vddc and vddio are available before initiating pcie accesses. note: vbat should not rise 10%?90% faster than 40 microseconds. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. sequencing of reset and regulator control signals BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 152 control signal timing diagrams figure 44: wlan = on, bluetooth = on figure 45: wlan = off, bluetooth = off 32.678 khz sleep clock vbat* vddio wl_reg_on bt_reg_on 90% of vh ~ 2 sleep cycles *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. vbat* vddio wl_reg_on bt_reg_on 32.678 khz sleep clock *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. sequencing of reset and regulator control signals BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 153 figure 46: wlan = on, bluetooth = off figure 47: wlan = off, bluetooth = on vbat* vddio wl_reg_on bt_reg_on 90% of vh ~ 2 sleep cycles 32.678 khz sleep clock *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. vbat* vddio wl_reg_on bt_reg_on 90% of vh ~ 2 sleep cycles 32.678 khz sleep clock *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. package information BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 154 section 22: package information package thermal characteristics junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi?j t ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta?j c ( ? jc ). the reason for this is that ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bottom and sides of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x ? jt where: ?t j = junction temperature at steady-state condition (c) ?t t = package case top center temperature at steady-state condition (c) ? p = device power dissipation (watts) ? ? jt = package thermal characteristics; no airflow (c/w) environmental characteristics for environmental characteristics data, see table 25: ?environmental ratings,? on page 98 . table 64: package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate, based on a 4-layer pcb that conforms to eia/jesd51?7 (101.6 mm 101.6 mm 1.6 mm) and p = 1.119w continuous dissipation. characteristic wlbga ? ja (c/w) (value in still air) 38.73 ? jb (c/w) 1.97 ? jc (c/w) 3.16 ? jt (c/w) 9.3 ? jb (c/w) 16.21 maximum junction temperature t j (c) 123.6 maximum power dissipation (w) 1.38 mechanical information BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 155 section 23: mechanical information figure 48: 140-ball wlbga package mechanical information mechanical information BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 156 figure 49: 140-balls wlbga keep-out areas for pcb layout?top view with balls facing down note: no top-layer metal is allowed in keep-out areas. note: a dxf file for the wlbga keep-out area is available for importation into a layout program. contact your broadcom fae for more information. keep out # horizental (mm) vertical (mm) 1 0.11 0.11 2 0.09 0.09 3 0.12 0.12 4 0.08 0.08 5 0.08 0.08 6 0.20 0.20 7 0.15 0.15 8 0.14 0.14 9 0.17 0.14 10 0.05 0.05 11 0.15 0.15 12 0.27 0.27 13 0.16 0.16 14 0.15 0.15 15 0.18 0.18 16 0.13 0.10 17 0.13 0.13 18 0.13 0.13 19 0.18 0.18 20 0.08 0.08 21 0.14 0.18 22 0.10 0.10 23 0.07 0.07 24 0.07 0.07 ordering information BCM43455 preliminary data sheet broadcom confidential broadcom ? november 5, 2015 ? 43455-ds109-r page 157 section 24: ordering information table 65: part ordering information part number package description operating ambient temperature BCM43455xkubg 140-ball wlbga (4.47 mm 5.27 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan+ bt 4.1 + fmrx ?30c to +85c BCM43455hkubg 140-ball wlbga (4.47 mm 5.27 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bt 4.1 + fmrx, bsp ?30c to +85c phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation. all rights reserved. 43455-ds109-r november 5, 2015 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. 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